摘要：【中文】本申请公开了一种抗腐蚀传送装置、传送装置的抗腐蚀方法，涉及半导体制造领域。该抗腐蚀传送装置至少包括传送装置、加热装置、温控器；所述加热装置设置在传送装置的外侧，所述加热装置用于加热所述传送装置；所述加热装置与所述温控器连接；解决了残留的腐蚀性气体与水汽接触后对传送装置造成腐蚀的问题；达到了避免腐蚀性气体腐蚀传送装置，提高传送装置使用寿命的效果。 【EN】The application discloses an anti-corrosion conveying device and an anti-corrosion method of the conveying device, and relates to the field of semiconductor manufacturing. The anti-corrosion conveying device at least comprises a conveying device, a heating device and a temperature controller; the heating device is arranged outside the conveying device and used for heating the conveying device; the heating device is connected with the temperature controller; the problem that the residual corrosive gas is in contact with water vapor and then corrodes the conveying device is solved; the conveying device is prevented from being corroded by corrosive gas, and the service life of the conveying device is prolonged.

摘要：【中文】本发明涉及半导体制造技术领域，具体涉及一显影方法和显影装置。其中，显影方法包括使曝光后的晶圆以第一速度旋转，辅助液喷头沿径向从晶圆的边缘区域处向晶圆的中心移动，辅助液喷头在移动过程中喷出辅助液；使晶圆提高旋转速度，显影液喷头在晶圆的中心区域喷出预湿显影液；使晶圆的旋转速度提高到第二速度，保持第二速度旋转第一时间段，扩展预湿显影液和辅助液以均匀润湿晶圆表面的光刻胶；对晶圆进行显影。显影装置包括旋转机构、显影液喷头、辅助液喷头以及用于输出控制信号的控制系统，控制信号用于控制旋转机构、显影液喷头和辅助液喷头执行显影方法。本发明通过预湿过程解决相关技术中显影过程中显影图案缺陷的问题。 【EN】The invention relates to the technical field of semiconductor manufacturing, in particular to a developing method and a developing device. The developing method comprises the steps that an exposed wafer rotates at a first speed, an auxiliary liquid spray head moves from the edge area of the wafer to the center of the wafer along the radial direction, and the auxiliary liquid spray head sprays auxiliary liquid in the moving process; the wafer is rotated at a higher speed, and the developing solution nozzle sprays pre-wetting developing solution in the central area of the wafer; increasing the rotation speed of the wafer to a second speed, keeping the second speed to rotate for a first time period, and expanding the pre-wetting developing solution and the auxiliary solution to uniformly wet the photoresist on the surface of the wafer; and developing the wafer. The developing device comprises a rotating mechanism, a developing liquid spray head, an auxiliary liquid spray head and a control system for outputting control signals, wherein the control signals are used for controlling the rotating mechanism, the developing liquid spray head and the auxiliary liquid spray head to execute a developing method. The invention solves the problem of developing pattern defects in the developing process in the related art through a pre-wetting process.

摘要：【中文】本发明公开了一种投影光刻系统的积分棒和刀口狭缝的防摩擦装置，刀口狭缝设置在积分棒的出光侧面的下游；刀口狭缝由上下左右4个档片设置；在积分棒的出光侧面上设置有距离传感器，用于实时监测积分棒和刀口狭缝之间的横向间距；控制电路接收距离传感器输出的横向间距，当距离传感器输出的横向间距在安全范围内时，投影光刻系统正常工作；当距离传感器输出的横向间距小于安全范围内时，控制电路使投影光刻系统停止工作。本发明还公开了一种投影光刻系统的积分棒和刀口狭缝的防摩擦方法。能防止积分棒和刀口狭缝产生摩擦，从而能提高光刻质量并能减少设备损伤。本发明能防止积分棒和刀口狭缝产生摩擦，从而能提高光刻质量并能减少设备损伤。 【EN】The invention discloses an anti-friction device of an integrating rod and a knife edge slit of a projection photoetching system, wherein the knife edge slit is arranged at the downstream of the light emergent side surface of the integrating rod; the knife edge slit is formed by 4 baffle sheets which are arranged up, down, left and right; a distance sensor is arranged on the light emergent side surface of the integrating rod and used for monitoring the transverse distance between the integrating rod and the knife edge slit in real time; the control circuit receives the transverse distance output by the distance sensor, and when the transverse distance output by the distance sensor is within a safe range, the projection lithography system works normally; when the transverse distance output by the distance sensor is smaller than the safety range, the control circuit stops the projection lithography system. The invention also discloses an anti-friction method for the integrating rod and the knife edge slit of the projection lithography system. The integrating rod and the knife edge slit can be prevented from generating friction, so that the photoetching quality can be improved, and the equipment damage can be reduced. The invention can prevent the integral rod and the knife edge slit from generating friction, thereby improving the photoetching quality and reducing the equipment damage.

摘要：【中文】本申请公开了一种金属互连结构的形成方法，包括：对晶圆进行除气和铜还原，该晶圆上形成有介质层，介质层中形成有通孔，除气和铜还原在同一腔体中进行，铜还原过程中通过加热促进铜还原反应；在通孔的侧壁沉积第一阻挡层；在第一阻挡层和介质层的表面沉积第二阻挡层；在第二阻挡层表面沉积铜籽晶；在铜籽晶表面形成铜金属层，铜金属层填充通孔。本申请通过在金属互连结构的形成过程中，将除气和铜还原在同一腔体中进行，且铜还原过程中通过加热促进铜还原反应，提高了铜还原的效率，从而能够提高晶圆表面产生的氧化铜的去除率，在一定程度上降低了器件的接触电阻。 【EN】The application discloses a forming method of a metal interconnection structure, which comprises the following steps: degassing and copper reduction are carried out on the wafer, a dielectric layer is formed on the wafer, a through hole is formed in the dielectric layer, the degassing and the copper reduction are carried out in the same cavity, and the copper reduction reaction is promoted by heating in the copper reduction process; depositing a first barrier layer on the side wall of the through hole; depositing a second barrier layer on the surfaces of the first barrier layer and the dielectric layer; depositing copper seed crystals on the surface of the second barrier layer; and forming a copper metal layer on the surface of the copper seed crystal, wherein the copper metal layer fills the through hole. This application is through in metal interconnect's formation process, go on degasification and copper reduction in same cavity, and promotes copper reduction reaction through the heating in the copper reduction process, has improved the efficiency that the copper was reduced to can improve the clearance of the copper oxide that the wafer surface produced, reduce the contact resistance of device to a certain extent.

摘要：【中文】本发明公开了一种开尔文结构的电阻测试方法，包括步骤：步骤一、提供开尔文测试结构，包括串联在一起的被测试电阻、第一寄生电阻和第二寄生电阻并形成有两个电压测试端和两个电流测试端；步骤二、在两个电流测试端施加第一电流，同时在两个电压测试端中测试第一电压；步骤三、在两个电流测试端施加和第一电流的方向相反的第二电流，同时在两个电压测试端中测试第二电压；步骤四、将第一电压减去第二电压的差值除以第一电流和第二电流的差值得到被测试电阻的最终测试值。本发明能降低电阻测试误差如由测试电压中的失调电压所产生的误差，从而使测试结果接近真实值。 【EN】The invention discloses a resistance testing method of a Kelvin structure, which comprises the following steps: providing a Kelvin test structure which comprises a tested resistor, a first parasitic resistor and a second parasitic resistor which are connected in series and forms two voltage test ends and two current test ends; step two, applying a first current to the two current test ends, and simultaneously testing a first voltage in the two voltage test ends; step three, applying a second current with the direction opposite to that of the first current to the two current testing ends, and simultaneously testing a second voltage in the two voltage testing ends; and step four, dividing the difference value of the first voltage minus the second voltage by the difference value of the first current and the second current to obtain the final test value of the tested resistor. The invention can reduce the resistance test error such as the error generated by the offset voltage in the test voltage, thereby leading the test result to be close to the true value.

摘要：【中文】本发明公开了一种CMOS图像传感器，包括感光区和逻辑区，感光区的各像素单元形成在第一有源区中，各像素单元包括感光二极管和多个MOS晶体管；逻辑区的MOS晶体管形成于对应的第二有源区中；在第一有源区的表面形成有SAB层，在各第二有源区的表面形成有第一自对准硅化物层；在穿过层间膜的接触孔的开口的底部表面和侧面依次形成有Ti层、第一TiN层和第二TiN层的叠加结构；Ti层和第一TiN层进行了RTP处理并在第一有源区的表面形成有TiSi，第二TiN将RTP处理后在第一TiN表面露出的Ti覆盖；在各接触孔的开口中填充有W层。本发明还公开了一种CMOS图像传感器的制造方法。本发明能在感光区的有源区表面不形成自对准硅化物的条件下，降低感光二极管的电流通路的电阻。 【EN】The invention discloses a CMOS image sensor, which comprises a photosensitive area and a logic area, wherein each pixel unit of the photosensitive area is formed in a first active area, and each pixel unit comprises a photosensitive diode and a plurality of MOS transistors; MOS transistors of the logic region are formed in the corresponding second active region; forming an SAB layer on the surface of the first active region, and forming a first self-aligned silicide layer on the surface of each second active region; sequentially forming a stacked structure of a Ti layer, a first TiN layer and a second TiN layer on the bottom surface and the side surface of the opening of the contact hole penetrating through the interlayer film; the Ti layer and the first TiN layer are subjected to RTP treatment, TiSi is formed on the surface of the first active region, and the Ti exposed on the surface of the first TiN layer after the RTP treatment is covered by the second TiN; the opening of each contact hole is filled with a W layer. The invention also discloses a manufacturing method of the CMOS image sensor. The invention can reduce the resistance of the current path of the photosensitive diode under the condition that the self-aligned silicide is not formed on the surface of the active region of the photosensitive region.

摘要：【中文】本发明提供一种监控沟槽深度的方法，包括量测沟槽刻蚀前产品的重量；对产品进行沟槽刻蚀；对刻蚀后的产品进行沟槽上开口CD量测；对刻蚀后的产品进行重量量测；依据产品刻蚀前后的重量、沟槽上开口CD大小以及硅质量密度计算所述沟槽的深度。能够有效实现产品在沟槽蚀刻工艺后的在线监控，具有实时在线监控的效果且有效避免产品报废，提高良率且节约生成成本。 【EN】The invention provides a method for monitoring the depth of a groove, which comprises the steps of measuring the weight of a product before the groove is etched; etching a groove on the product; measuring the CD of the opening on the groove of the etched product; measuring the weight of the etched product; and calculating the depth of the groove according to the weight of the product before and after etching, the size of the opening CD on the groove and the mass density of silicon. The on-line monitoring of the product after the groove etching process can be effectively realized, the effect of real-time on-line monitoring is achieved, the product scrapping is effectively avoided, the yield is improved, and the generation cost is saved.

摘要：【中文】本申请公开了一种光刻机对位方法，涉及半导体制造技术领域。该方法包括利用对位光斑周期性扫描晶圆上的对位标记，获取每条扫描路径对应的强度位置相关性图；根据强度位置相关性图，确定每条扫描路径对应的多重相关系数和晶圆对位信号强度；根据多重相关系数和晶圆对位信号强度，计算出每条扫描路径对应的评估值；将最大评估值对应的扫描路径确定为最佳扫描路径，最佳扫描路径用于定义对位标记的位置；评估值＝多重相关系数*多重相关系数*晶圆对位信号强度；解决了现有方式在选择最佳扫描路径时容易受到异常情况的影响，导致晶圆次品的问题；达到了减少对位信号受损或偏移的影响，提高最佳扫描路径选择的准确度，降低晶圆次品率的效果。 【EN】The application discloses a lithography machine alignment method, and relates to the technical field of semiconductor manufacturing. Periodically scanning alignment marks on a wafer by using alignment light spots to obtain an intensity position correlation diagram corresponding to each scanning path; determining multiple correlation coefficients and wafer alignment signal intensity corresponding to each scanning path according to the intensity position correlation diagram; calculating an evaluation value corresponding to each scanning path according to the multiple correlation coefficients and the wafer alignment signal intensity; determining the scanning path corresponding to the maximum evaluation value as an optimal scanning path, wherein the optimal scanning path is used for defining the position of the alignment mark; evaluating the wafer alignment signal intensity as multiple correlation coefficient; the problem that the existing method is easily influenced by abnormal conditions when the optimal scanning path is selected, so that defective wafers are caused is solved; the effects of reducing the influence of damage or deviation of alignment signals, improving the accuracy of selecting the optimal scanning path and reducing the defective rate of wafers are achieved.

摘要：【中文】本申请公开了一种MOSFET器件的制造方法，包括：提供一硅衬底，硅衬底上形成有硅氧化物层；通过光刻工艺在硅氧化物层上的预定区域覆盖光阻；通过ICP刻蚀设备对除预定区域以外的其它区域的硅氧化物层进行刻蚀，直至硅衬底暴露，通过调节ICP刻蚀设备的刻蚀参数使刻蚀过程中对硅氧化物的刻蚀速率大于对硅的刻蚀速率；通过ICP刻蚀设备对其它区域的硅衬底进行刻蚀，形成沟槽，通过调节刻蚀过程中的参数控制每个沟槽之间均一性。本申请通过ICP刻蚀设备对MOSFET器件的硅氧化物层和硅衬底进行刻蚀，降低了MOSFET器件的制造工艺的复杂度。 【EN】The application discloses a manufacturing method of a MOSFET device, which comprises the following steps: providing a silicon substrate, wherein a silicon oxide layer is formed on the silicon substrate; covering a photoresist on a predetermined region on the silicon oxide layer by a photolithography process; etching the silicon oxide layer of the other region except the predetermined region by ICP etching equipment until the silicon substrate is exposed, and adjusting the etching parameters of the ICP etching equipment to enable the etching rate of the silicon oxide to be greater than that of the silicon in the etching process; etching the silicon substrate in other areas by ICP etching equipment to form grooves, and controlling the uniformity among the grooves by adjusting parameters in the etching process. According to the method, the silicon oxide layer and the silicon substrate of the MOSFET device are etched through the ICP etching equipment, so that the complexity of the manufacturing process of the MOSFET device is reduced.

摘要：【中文】本申请公开了一种边缘多余膜层刻蚀一体化装置及方法，涉及半导体设备制造领域。该装置至少包括腔体、静电吸附盘、可升降边缘环、至少2组阻挡片支撑组件；静电吸附盘和可升降边缘环设置在腔体内，可升降边缘环设置在静电吸附盘的外侧；至少2组阻挡片支撑组件设置在可升降边缘环的外侧，至少2组阻挡片支撑组件用于交替承载阻挡片；其中，每组阻挡片支撑组件包括至少3个阻挡片支撑组件，每个阻挡片支撑组件包括阻挡片支撑架、阻挡片支撑架旋转升降装置，阻挡片支撑架与阻挡片支撑架旋转升降装置连接；解决了现有技术中刻蚀晶圆边缘工序多、成本高的问题；达到了一体化刻蚀晶圆的有效图形区域和边缘，提高良率，降低成本的效果。 【EN】The application discloses an edge redundant film layer etching integrated device and method, and relates to the field of semiconductor equipment manufacturing. The device at least comprises a cavity, an electrostatic adsorption disc, a liftable edge ring and at least 2 groups of barrier plate supporting assemblies; the electrostatic adsorption disc and the liftable edge ring are arranged in the cavity, and the liftable edge ring is arranged on the outer side of the electrostatic adsorption disc; the at least 2 groups of barrier plate supporting assemblies are arranged on the outer side of the liftable edge ring, and the at least 2 groups of barrier plate supporting assemblies are used for alternately bearing barrier plates; each group of the barrier piece supporting assemblies comprises at least 3 barrier piece supporting assemblies, each barrier piece supporting assembly comprises a barrier piece supporting frame and a barrier piece supporting frame rotary lifting device, and the barrier piece supporting frames are connected with the barrier piece supporting frame rotary lifting devices; the problems of multiple procedures and high cost of etching the edge of the wafer in the prior art are solved; the effects of integrally etching the effective pattern area and the edge of the wafer, improving the yield and reducing the cost are achieved.