摘要：【中文】本发明提供一种基板结构以及半导体封装，所述基板结构包括核心层、第一内部芯片、第一线路结构以及第一绝缘层。核心层包括第一表面。第一内部芯片设置于核心层的第一表面上。第一线路结构包括第一图案化导电层及第一导通柱。第一图案化导电层设置于核心层的第一表面上。第一导通柱设置于第一图案化导电层上，并与第一内部芯片电性连接。第一绝缘层覆盖核心层的第一表面、第一内部芯片、第一图案化导电层及部分的第一导通柱，并暴露出第一导通柱上表面，而形成第一接垫。 【EN】The invention provides a substrate structure and a semiconductor package. The core layer includes a first surface. The first internal chip is disposed on the first surface of the core layer. The first circuit structure includes a first patterned conductive layer and a first conductive via. The first patterned conductive layer is disposed on the first surface of the core layer. The first conductive via is disposed on the first patterned conductive layer and electrically connected to the first internal chip. The first insulating layer covers the first surface of the core layer, the first internal chip, the first patterned conductive layer and part of the first conductive via, and exposes the upper surface of the first conductive via to form a first pad.

摘要：【中文】本发明提供一种边缘缺陷检查方法，包括以下步骤：获取一目标元件的外观以取得一外观图像；依据外观图像决定出多个参考点；依据参考点形成一识别图案；以及依据识别图案及外观图像产生一检查结果。 【EN】The invention provides an edge defect inspection method, which comprises the following steps: acquiring the appearance of a target element to obtain an appearance image; determining a plurality of reference points according to the appearance image; forming an identification pattern according to the reference point; and generating an inspection result according to the identification pattern and the appearance image.

摘要：【中文】本发明提供一种半导体封装结构及其制作方法，所述制作方法包括：提供导线架，包括第一引脚群与第二引脚群。设置载体于第一引脚群的一侧，其中第一引脚群包括多个第一引脚，且载体覆盖任二相邻的第一引脚之间的间隙。形成两阶段热固性胶层于第一引脚群的另一侧，两阶段热固性胶层进一步填入任二相邻的第一引脚之间的间隙。使第一芯片贴合于两阶段热固性胶层，且第一芯片与载体分别位于第一引脚群的相对两侧。采用打线接合的方式使第一芯片电性连接第一引脚群与第二引脚群。形成封装胶体，以包覆导线架、两阶段热固性胶层及第一芯片。 【EN】The invention provides a semiconductor packaging structure and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: a lead frame is provided, which includes a first lead group and a second lead group. The carrier is arranged on one side of the first pin group, wherein the first pin group comprises a plurality of first pins, and the carrier covers a gap between any two adjacent first pins. And forming a two-stage thermosetting adhesive layer on the other side of the first pin group, wherein the two-stage thermosetting adhesive layer is further filled into a gap between any two adjacent first pins. The first chip is attached to the two-stage thermosetting adhesive layer, and the first chip and the carrier are respectively located on two opposite sides of the first pin group. The first chip is electrically connected with the first pin group and the second pin group by adopting a wire bonding mode. And forming an encapsulation colloid to coat the lead frame, the two-stage thermosetting adhesive layer and the first chip.