摘要：【中文】本公开提供了一种半导体器件的形成方法。本公开实施例对形成连接源区、漏区和栅极结构与互连结构的导电结构的方法进行改进，使连接到源区和漏区的第一导电结构和第二导电结构与连接到栅极结构的第三导电结构在不同的步骤中形成，避免现有工艺过程中栅极结构与导电结构间形成缺陷而导致接触电阻异常，进而导致半导体器件失效的问题，同时，还能够避免连接栅极结构、连接源区和连接漏区的导电结构之间的距离过近而形成短路，提高半导体器件的良率。 【EN】The present disclosure provides a method of forming a semiconductor device. The embodiment of the disclosure improves a method for forming a conductive structure for connecting a source region, a drain region, a gate structure and an interconnection structure, so that a first conductive structure and a second conductive structure connected to the source region and the drain region and a third conductive structure connected to the gate structure are formed in different steps, the problem that in the prior art, contact resistance is abnormal due to defects formed between the gate structure and the conductive structures, and further a semiconductor device fails is solved, meanwhile, short circuit caused by too close distance among the conductive structures connected with the gate structure, the source region and the drain region can be avoided, and the yield of the semiconductor device is improved.

摘要：【中文】本发明涉及半导体制造工艺设计领域，提供了一种垂直式环绕栅极场效应晶体管的制造方法，采用气‑液‑固方法制得所述垂直式环绕栅极场效应晶体管的纳米线。采用气‑液‑固方法不仅能够得到晶格结构完整、尺寸均一可控的纳米线，且制备工艺成熟稳定、成本较低。此外，气‑液‑固方法还能够在生长纳米线的过程中进行原位掺杂，进一步简化工艺，提高产能。 【EN】The invention relates to the field of semiconductor manufacturing process design, and provides a method for manufacturing a vertical surrounding grid field effect transistor. The gas-liquid-solid method is adopted, so that the nanowire with complete lattice structure and uniform and controllable size can be obtained, the preparation process is mature and stable, and the cost is lower. In addition, the gas-liquid-solid method can also carry out in-situ doping in the process of growing the nanowire, further simplify the process and improve the productivity.

摘要：【中文】本发明提供了一种硅通孔结构的形成方法、CIS晶圆的形成方法及CIS晶圆，包括提供晶圆键合结构，所述像素晶圆中的第一层叠层中形成有第一顶层金属层及第一阻挡层，所述第一阻挡层覆盖部分所述第一顶层金属层，当刻蚀所述晶圆键合结构以形成硅通孔时，所述像素晶圆的第一阻挡层可以保护其顶层金属不被刻蚀，刻蚀停止在暴露出所述逻辑晶圆的第二顶层金属层，所以，形成的开口可以同时暴露出第一顶层金属层和第二顶层金属层。本发明提供的硅通孔结构的形成方法及CIS晶圆的形成方法可以通过一步刻蚀形成开口，简化了工艺，节约了光罩，并且降低了制造的成本和时间。 【EN】The invention provides a forming method of a silicon through hole structure, a forming method of a CIS wafer and the CIS wafer, wherein the forming method comprises the steps of providing a wafer bonding structure, forming a first top metal layer and a first barrier layer in a first laminated layer in a pixel wafer, covering a part of the first top metal layer by the first barrier layer, and when the wafer bonding structure is etched to form a silicon through hole, the first barrier layer of the pixel wafer can protect top metal from being etched and the etching is stopped at a second top metal layer exposing a logic wafer, so that a formed opening can simultaneously expose the first top metal layer and the second top metal layer. The forming method of the through silicon via structure and the forming method of the CIS wafer can form the opening through one-step etching, simplify the process, save the photomask and reduce the manufacturing cost and time.

摘要：【中文】本公开提供了一种半导体器件的形成方法。本公开实施例对在中通孔的工艺制程中半导体衬底的背面露出硅通孔中导电层的方法进行改进，减小现有工艺过程中研磨减薄工艺去除半导体衬底的尺寸，增加选择性刻蚀工艺去除半导体衬底的尺寸。由此，不需要同时研磨半导体衬底和导电层，避免导电层中的导电材料离子向半导体衬底中扩散，提高产品的良率。 【EN】The present disclosure provides a method of forming a semiconductor device. The embodiment of the disclosure improves the method for exposing the conducting layer in the through silicon via on the back surface of the semiconductor substrate in the process of the through hole, reduces the size of the semiconductor substrate removed by the grinding and thinning process in the existing process, and increases the size of the semiconductor substrate removed by the selective etching process. Therefore, the semiconductor substrate and the conducting layer do not need to be ground at the same time, the conducting material ions in the conducting layer are prevented from diffusing into the semiconductor substrate, and the yield of products is improved.