摘要：【中文】本发明提供了一种板级晶圆扇入封装方法，包括以下步骤：S101、在一封装载板至少一面上粘贴键合胶层，并将至少一个晶圆粘贴在键合胶层上；S102、在至少一个晶圆的远离所述键合胶层的面上进行塑封；S103、去除靠近所述至少一个晶圆的键合胶层以及所述封装载板；S104、基于晶圆上的晶片定位线确定曝光显影的位置，并基于所述曝光显影的位置在所述晶圆的远离塑封层的一面制备金属线路层。本发明采用板级技术实现晶圆整体扇入封装，可实现同时封装单片或多片晶圆的扇入封装，单板产出封装器件数量和效率是传统晶圆扇入封装的几倍；晶圆整体封装可以有效地避免划片、单芯片贴片等工艺以及塑封过程中芯片偏移等问题，进而提高封装的可靠性，同时实现成本的降低。 【EN】The invention provides a board-level wafer fan-in packaging method, which comprises the following steps: s101, pasting a bonding adhesive layer on at least one surface of a packaging carrier plate, and pasting at least one wafer on the bonding adhesive layer; s102, performing plastic package on the surface, far away from the bonding glue layer, of at least one wafer; s103, removing the bonding glue layer close to the at least one wafer and the packaging carrier plate; s104, determining an exposure and development position based on a chip positioning line on the wafer, and preparing a metal circuit layer on one surface of the wafer far away from the plastic package layer based on the exposure and development position. The invention adopts the plate-level technology to realize the integral fan-in packaging of the wafer, can realize the fan-in packaging of a single wafer or a plurality of wafers simultaneously, and has the advantages that the quantity and the efficiency of single-plate output packaging devices are several times of those of the traditional wafer fan-in packaging; the wafer overall packaging can effectively avoid the problems of processes such as scribing, single chip mounting and the like, chip offset in the plastic packaging process and the like, so that the packaging reliability is improved, and meanwhile, the cost is reduced.

摘要：【中文】本发明公开一种TMV结构的制备方法，包括以下步骤：提供芯片塑封板，在芯片塑封板的非芯片区域沿芯片塑封板的厚度方向开设盲孔；在盲孔内填充金属填充柱；对芯片塑封板远离盲孔开口的一侧面进行研磨抛光处理，使金属填充柱远离该侧面的一端与芯片塑封板的表面平齐，形成TMV结构。本发明可制得高质量、高可靠性的TMV结构，与传统的TMV结构采用通孔沉积制备方法相比，盲孔填充成本低，可改善TMV结构通孔填充缝隙问题，降低虚填概率，提高封装质量与可靠性，降低生产成本；本发明还公开了大板扇出型异构集成封装结构的制备方法，采用该方法可制得低成本、小型化、高集成度的大板扇出型异构集成封装结构，可提高垂直互连结构的可靠性。 【EN】The invention discloses a preparation method of a TMV structure, which comprises the following steps: providing a chip plastic sealing plate, and forming blind holes in a non-chip area of the chip plastic sealing plate along the thickness direction of the chip plastic sealing plate; filling metal filling columns in the blind holes; and grinding and polishing one side surface of the chip plastic sealing plate, which is far away from the blind hole opening, so that one end of the metal filling column, which is far away from the side surface, is flush with the surface of the chip plastic sealing plate, and a TMV structure is formed. Compared with the traditional TMV structure adopting a through hole deposition preparation method, the blind hole filling cost is low, the problem of filling gaps of the TMV structure through holes can be solved, the dummy filling probability is reduced, the packaging quality and reliability are improved, and the production cost is reduced; the invention also discloses a preparation method of the large-board fan-out heterogeneous integrated packaging structure, and the large-board fan-out heterogeneous integrated packaging structure with low cost, miniaturization and high integration can be prepared by adopting the method, so that the reliability of the vertical interconnection structure can be improved.

摘要：【中文】本发明提供一种改善埋入式扇出型封装结构电镀性能的制作方法，包括以下步骤：提供一载板，对载板进行开槽，形成槽孔，然后在载板计划制作电镀孔的位置打通孔；将载板贴在承载胶上，将芯片植入槽孔内，并在通孔内植入金属块；进行第一次塑封，形成一次塑封件；拆除承载胶，把一次塑封件上下翻转，对一次塑封件的另一面进行第二次塑封，形成二次塑封件；在第一塑封层和第二塑封层上打盲孔，以露出芯片的IO接口和金属块；对盲孔进行真空溅射，并在二次塑封件的上、下两面建立种子层；依次通过贴干膜‑曝光‑显影‑闪蚀，制作RDL层。本发明的改善埋入式扇出型封装结构电镀性能的制作方法有效降低电镀的工艺难度，缩短电镀的时间，降低生产成本。 【EN】The invention provides a manufacturing method for improving electroplating performance of an embedded fan-out packaging structure, which comprises the following steps: providing a carrier plate, slotting the carrier plate to form a slotted hole, and then punching a through hole at the position of the carrier plate where a plating hole is planned to be manufactured; attaching the carrier plate to the carrier glue, implanting the chip into the slot hole, and implanting a metal block into the through hole; carrying out primary plastic package to form a primary plastic package part; removing the bearing glue, turning the primary plastic package piece up and down, and carrying out secondary plastic package on the other side of the primary plastic package piece to form a secondary plastic package piece; drilling blind holes on the first plastic packaging layer and the second plastic packaging layer to expose an IO interface and a metal block of the chip; carrying out vacuum sputtering on the blind hole, and establishing seed layers on the upper surface and the lower surface of the secondary plastic package part; and sequentially carrying out dry film pasting, exposure, development and flash etching to prepare the RDL layer. The manufacturing method for improving the electroplating performance of the embedded fan-out type packaging structure effectively reduces the difficulty of the electroplating process, shortens the electroplating time and reduces the production cost.

摘要：【中文】本发明公开一种扇出型三维封装结构及其制备方法，该制备方法包括：提供埋入材料，在埋入材料上开设第一通孔和第二通孔，然后贴到第一承载胶上；提供第一芯片，将第一芯片贴装于第一通孔内，并在第二通孔内植入导电柱；采用塑封料于埋入材料靠近第一芯片的正面的一侧进行塑封，形成第一塑封层；拆除第一承载胶，翻转第一塑封层并固定；提供第二芯片，将第二芯片贴装于第一芯片的背面，采用引线连接第二芯片的I/O接口和导电柱；采用塑封料于埋入材料远离第一塑封层的一侧进行塑封，形成第二塑封层；在第一塑封层上制作种子层和重布线层，并在重布线层的焊盘区植入金属凸块。本发明有效降低了扇出型三维封装结构的封装高度和生产成本。 【EN】The invention discloses a fan-out type three-dimensional packaging structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing an embedding material, forming a first through hole and a second through hole in the embedding material, and then pasting the embedding material on the first bearing glue; providing a first chip, mounting the first chip in the first through hole, and implanting a conductive column in the second through hole; plastic packaging is carried out on one side, close to the front side of the first chip, of the embedded material by adopting a plastic packaging material to form a first plastic packaging layer; removing the first bearing glue, and turning over and fixing the first plastic packaging layer; providing a second chip, mounting the second chip on the back surface of the first chip, and connecting an I/O interface and a conductive column of the second chip by adopting a lead; plastic packaging is carried out on one side, far away from the first plastic packaging layer, of the embedded material by adopting a plastic packaging material to form a second plastic packaging layer; and manufacturing a seed layer and a rewiring layer on the first plastic packaging layer, and implanting a metal bump in a pad area of the rewiring layer. The invention effectively reduces the packaging height and the production cost of the fan-out type three-dimensional packaging structure.

摘要：【中文】本发明公开一种具有高散热和电磁屏蔽性的扇出型封装结构及其制备方法，其中，该制备方法包括以下步骤：将芯片贴装于载板上；提供金属材质的散热屏蔽结构，具有背向设置的凹槽和栅格，将散热屏蔽结构贴装于载板上，使芯片位于凹槽内并通过散热胶与凹槽连接；采用塑封料对散热屏蔽结构进行选择性塑封，形成覆盖散热屏蔽结构的外周并使栅格外露的塑封件；移除载板，翻转塑封件，依次制作种子层和重布线层，并在重布线层的焊盘区植入金属凸块。本发明可以有效屏蔽外部的电磁干扰，保证芯片工作的稳定性和可靠性，芯片工作时产生的热量通过具有较大表面积的栅格进行快速散热，同时还能防止重布线层与芯片的I/O接口之间的结合力受到影响。 【EN】The invention discloses a fan-out type packaging structure with high heat dissipation and electromagnetic shielding performance and a preparation method thereof, wherein the preparation method comprises the following steps: mounting the chip on a carrier plate; providing a metal radiating and shielding structure which is provided with a groove and a grid which are arranged in a back-to-back manner, and attaching the radiating and shielding structure on a carrier plate to enable a chip to be positioned in the groove and connected with the groove through radiating glue; selectively plastically packaging the heat dissipation shielding structure by adopting a plastic packaging material to form a plastic packaging piece which covers the periphery of the heat dissipation shielding structure and exposes the grids; and removing the carrier plate, turning over the plastic package part, sequentially manufacturing the seed layer and the rewiring layer, and implanting a metal bump in the pad area of the rewiring layer. The invention can effectively shield external electromagnetic interference, ensure the working stability and reliability of the chip, quickly dissipate heat generated by the chip during working through the grid with larger surface area, and simultaneously prevent the bonding force between the rewiring layer and the I/O interface of the chip from being influenced.

摘要：【中文】本发明提供一种三维异构AIP芯片的封装方法及封装结构，封装方法包括：在晶圆的正面贴研磨胶带，并对其背面研磨减薄；对晶圆划片处理形成毫米波芯片；将毫米波芯片贴在临时键合胶上，在毫米波芯片的上表面涂覆第一石墨烯层，在第一石墨烯层上涂布反射层；对毫米波芯片、第一石墨烯层和反射层进行塑封；于第一塑封层形成通孔，把Cu填满通孔；在一次塑封件的上表面制作上线路层；在上线路层上放置IPD芯片并布设天线层，涂覆第二石墨烯层，对上线路层、IPD芯片、天线层、第二石墨烯层进行塑封；在二次塑封件的下表面制作下线路层，在下线路层上植锡球。本发明的三维异构AIP芯片的封装方法及封装结构的散热性能和稳定性良好。 【EN】The invention provides a packaging method and a packaging structure of a three-dimensional heterogeneous AIP chip, wherein the packaging method comprises the following steps: pasting a grinding adhesive tape on the front side of the wafer, and grinding and thinning the back side of the wafer; carrying out scribing treatment on the wafer to form a millimeter wave chip; pasting the millimeter wave chip on the temporary bonding adhesive, coating a first graphene layer on the upper surface of the millimeter wave chip, and coating a reflecting layer on the first graphene layer; plastically packaging the millimeter wave chip, the first graphene layer and the reflecting layer; forming a through hole in the first plastic package layer, and filling the through hole with Cu; manufacturing an upper circuit layer on the upper surface of the primary plastic package part; placing an IPD chip and an antenna layer on the upper line layer, coating a second graphene layer, and plastically packaging the upper line layer, the IPD chip, the antenna layer and the second graphene layer; and manufacturing a lower circuit layer on the lower surface of the secondary plastic package part, and planting solder balls on the lower circuit layer. The packaging method and the packaging structure of the three-dimensional heterogeneous AIP chip have good heat dissipation performance and stability.

摘要：【中文】本发明公开一种降低扇出型封装应力的方法及其应用的塑封模具，其中，降低扇出型封装应力的方法包括步骤：提供塑封模具，在塑封模具的塑封槽的槽底与预塑封的芯片错开的位置凸设若干冷却针，并使冷却针的长度小于塑封槽的深度，采用塑封模具对贴装于载板上的若干芯片进行塑封。本发明在塑封模具的塑封槽的槽底增设冷却针，合模固化时，冷却针深入塑封料中，在塑封料冷却过程中，冷却针可以加快塑封料内部的冷却速度，从而平衡塑封料内外的冷却速度，使塑封料整体的冷却速度基本保持一致，以减小塑封料的内应力，从而有效减少扇出型芯片封装结构的翘曲。 【EN】The invention discloses a method for reducing fan-out type packaging stress and a plastic packaging mold applied by the same, wherein the method for reducing fan-out type packaging stress comprises the following steps: providing a plastic package mold, convexly arranging a plurality of cooling pins at staggered positions of the bottom of a plastic package groove of the plastic package mold and a chip to be subjected to plastic package, enabling the length of the cooling pins to be smaller than the depth of the plastic package groove, and carrying out plastic package on the plurality of chips attached to the carrier plate by adopting the plastic package mold. According to the invention, the cooling needle is additionally arranged at the bottom of the plastic packaging groove of the plastic packaging mold, when the mold is closed and solidified, the cooling needle extends into the plastic packaging material, and in the cooling process of the plastic packaging material, the cooling needle can accelerate the cooling speed inside the plastic packaging material, so that the cooling speed inside and outside the plastic packaging material is balanced, the cooling speed of the whole plastic packaging material is basically kept consistent, the internal stress of the plastic packaging material is reduced, and the warping of the fan-out chip packaging structure is effectively reduced.

摘要：【中文】本发明公开一种基于刚性框架的TMV扇出型封装结构，包括：具有矩形结构的金属框架和位于金属框架的矩形框内的芯片组；塑封层，包覆金属框架和芯片组，塑封层沿其厚度方向具有背向设置的第一面和第二面；位于塑封层的第一面的第一电连接结构和与第一电连接结构电气连接的第一金属凸块；位于塑封层的第二面的第二电连接结构和与第二电连接结构电气连接的第二金属凸块；芯片组的I/O接口与第一电连接结构或第二电连接结构电气连接，金属框架的一端面与第一电连接结构电气连接，另一端面与第二电连接结构电气连接。本发明可大幅降低扇出型封装结构的翘曲，提高芯片散热效果，并能简化上下层电气导通工艺，降低生产成本。 【EN】The invention discloses a TMV fan-out type packaging structure based on a rigid frame, which comprises: the chip set comprises a metal frame with a rectangular structure and a chip set positioned in the rectangular frame of the metal frame; the plastic packaging layer wraps the metal frame and the chip set, and is provided with a first surface and a second surface which are arranged in a back direction along the thickness direction of the plastic packaging layer; the first electrical connection structure is positioned on the first surface of the plastic packaging layer, and the first metal bump is electrically connected with the first electrical connection structure; the second electrical connection structure is positioned on the second surface of the plastic packaging layer, and the second metal bump is electrically connected with the second electrical connection structure; the I/O interface of the chip set is electrically connected with the first electric connection structure or the second electric connection structure, one end face of the metal frame is electrically connected with the first electric connection structure, and the other end face of the metal frame is electrically connected with the second electric connection structure. The invention can greatly reduce the warpage of the fan-out type packaging structure, improve the heat dissipation effect of the chip, simplify the electrical conduction process of the upper layer and the lower layer and reduce the production cost.

摘要：【中文】本发明公开一种低RDSON三维堆叠集成封装结构及其制备方法，其中，制备方法包括以下步骤：提供载板，于载板一侧依次贴装导电材料和第一阻焊层，对第一阻焊层开孔，并于开孔处分别涂覆锡膏；于锡膏处贴装具有双面I/O口的第一芯片及导电块，塑封后制作第一重布线层；拆键合并翻转固定，对导电材料蚀刻，形成第二重布线层；于第二重布线层一侧制作第二阻焊层，并对第二阻焊层对应导电块位置开孔；于第二阻焊层一侧贴装第二芯片，采用引线连接第二芯片的I/O口和第二重布线层，并对第二芯片进行塑封。本发明有效降低了RDSON，减小了封装尺寸，提高了系统集成度，避免TMV结构产生空洞现象，降低了电镀工艺难度，降低了生产成本。 【EN】The invention discloses a low RDSON three-dimensional stacking integrated packaging structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a carrier plate, sequentially pasting a conductive material and a first solder mask layer on one side of the carrier plate, opening holes in the first solder mask layer, and respectively coating solder paste on the positions of the openings; mounting a first chip with a double-sided I/O port and a conductive block at the position of the solder paste, and manufacturing a first rewiring layer after plastic packaging; removing the bonding, overturning and fixing, and etching the conductive material to form a second rewiring layer; manufacturing a second solder mask layer on one side of the second rewiring layer, and opening holes in the positions, corresponding to the conductive blocks, of the second solder mask layer; and pasting a second chip on one side of the second solder mask layer, connecting the I/O port of the second chip and the second rewiring layer by adopting a lead, and plastically packaging the second chip. The invention effectively reduces RDSON, reduces the packaging size, improves the system integration level, avoids the phenomenon of generating cavities in the TMV structure, reduces the difficulty of the electroplating process and reduces the production cost.