摘要：【中文】本发明实施例公开了一种位线电压的施加方法、装置、存储设备和存储介质。所述方法包括：编程过程中，当施加在选中字线上的编程电压脉冲信号中的每一个编程电压脉冲结束时，检测选中字线中的编程单元的导通阈值是否大于等于位线加压阈值且小于编程检验电压阈值；如果编程单元的导通阈值大于等于位线电压阈值且小于编程检验电压阈值，则在向选中字线施加下一个编程电压脉冲时，同时向编程单元对应的位线施加位线电压脉冲信号中的第一个位线电压脉冲。本发明实施例的技术方案实现了有效控制快速编程存储单元的编程速度，降低了编程结束时，快速编程存储单元与慢速编程存储单元的最大阈值差值，从而有效缩小了一个page在被编程之后的阈值电压分布宽度。 【EN】The embodiment of the invention discloses a bit line voltage applying method, a bit line voltage applying device, storage equipment and a storage medium. The method comprises the following steps: detecting whether the conduction threshold of the programming unit in the selected word line is more than or equal to the bit line pressurization threshold and less than the programming verification voltage threshold when each programming voltage pulse in the programming voltage pulse signal applied to the selected word line is ended in the programming process; and if the conduction threshold of the programming unit is greater than or equal to the bit line voltage threshold and less than the program verification voltage threshold, simultaneously applying the first bit line voltage pulse in the bit line voltage pulse signals to the bit line corresponding to the programming unit when applying the next program voltage pulse to the selected word line. The technical scheme of the embodiment of the invention realizes the effective control of the programming speed of the fast programming storage unit, and reduces the maximum threshold difference value between the fast programming storage unit and the slow programming storage unit when the programming is finished, thereby effectively reducing the threshold voltage distribution width of a page after being programmed.

摘要：【中文】本发明提供一种低压差线性稳压器和控制系统，涉及电子领域。所述低压差线性稳压器包括：控制电路、电压调整电路以及功能控制脚；控制电路与低压差线性稳压器的电压输入端、低压差线性稳压器的电压输出端、电压调整电路以及功能控制脚分别电连接；电压调整电路与低压差线性稳压器的电压输出端电连接；控制电路的工作状态根据功能控制脚上的控制电平确定；低压差线性稳压器的输出电压根据控制电路的工作状态确定。本发明的低压差线性稳压器，只增加了一个功能控制脚和一个控制电路，增加的元器件极少，在保证了低压差线性稳压器安全可靠使用的同时，成本又比较低廉且可拓展性强，低压差线性稳压器可以应用的范围得到了扩展。 【EN】The invention provides a low dropout regulator and a control system, and relates to the field of electronics. The low dropout regulator comprises: the control circuit, the voltage regulating circuit and the function control pin; the control circuit is electrically connected with a voltage input end of the low dropout linear regulator, a voltage output end of the low dropout linear regulator, the voltage adjusting circuit and the functional control pin respectively; the voltage adjusting circuit is electrically connected with the voltage output end of the low dropout linear regulator; the working state of the control circuit is determined according to the control level on the functional control pin; the output voltage of the low dropout regulator is determined according to the working state of the control circuit. The low dropout linear regulator only adds one functional control pin and one control circuit, the added components are few, the low dropout linear regulator is ensured to be safely and reliably used, the cost is low, the expansibility is strong, and the applicable range of the low dropout linear regulator is expanded.

摘要：【中文】本发明实施例提供了一种振荡器电路及非易失存储器，电路包括了延时反相单元、选择锁存单元、与非门单元、非门单元、P型场效应管：P10。本发明实施例中，通过选择锁存单元将与非门单元的第三输出端的信号和非门单元的输出端的信号，经过选择和锁存处理后，使得当EN出现下降沿时，选择锁存单元可以将第二输出端的输出信号锁存在下降沿出现前的状态，因此能有效避免时钟电路中的毛刺，输出完整无毛刺的时钟信号。 【EN】The embodiment of the invention provides an oscillator circuit and a nonvolatile memory, wherein the circuit comprises a time delay inverting unit, a selection latch unit, a NAND gate unit, a NOT gate unit and a P-type field effect transistor: p10. In the embodiment of the invention, after the selection and latch unit selects and latches the signal of the third output end of the NAND gate unit and the signal of the output end of the NOT gate unit, when EN has a falling edge, the selection latch unit can latch the output signal of the second output end in a state before the falling edge occurs, so that the glitch in the clock circuit can be effectively avoided, and a complete glitch-free clock signal is output.

摘要：【中文】本发明实施例提供了一种电荷泵系统和非易失存储器，该系统包括：振荡器单元、第一电荷泵单元、第二电荷泵单元；第一延时反相锁存电路的输出端与第二延时反相锁存电路的输入端、第一电荷泵单元的输入端连接；第二延时反相锁存电路的输出端与反相器的输入端、第二电荷泵单元的输入端连接；第一延时反相锁存电路包括第一锁存使能端，第二延时反相锁存电路包括第二锁存使能端；第一锁存使能端与第一锁存使能端连接；第一电荷泵单元的输出端与第二电荷泵单元的输出端连接。本发明实施例中，将振荡器单元的两路无毛刺的时钟信号分别输入到第一电荷泵单元和第二电荷泵单元，使得系统响应速度非常快，且由于时钟信号无毛刺，可以避免发生过冲现象。 【EN】An embodiment of the present invention provides a charge pump system and a nonvolatile memory, where the system includes: the charge pump comprises an oscillator unit, a first charge pump unit and a second charge pump unit; the output end of the first delay inverting latch circuit is connected with the input end of the second delay inverting latch circuit and the input end of the first charge pump unit; the output end of the second time delay inverting latch circuit is connected with the input end of the phase inverter and the input end of the second charge pump unit; the first time-delay inverting latch circuit comprises a first latch enabling end, and the second time-delay inverting latch circuit comprises a second latch enabling end; the first latch enabling end is connected with the first latch enabling end; the output end of the first charge pump unit is connected with the output end of the second charge pump unit. In the embodiment of the invention, two paths of glitch-free clock signals of the oscillator unit are respectively input into the first charge pump unit and the second charge pump unit, so that the response speed of the system is very high, and the overshoot phenomenon can be avoided because the clock signals are glitch-free.

摘要：【中文】本发明实施例提供了一种充放电电路及振荡器，该充放电电路包括：参考电压产生单元、充电单元、放电单元；参考电压产生单元用于在参考电压产生单元产生参考电压后，通过参考电压输出端输出；放电单元用于根据时钟输入端接收到的时钟信号，在比较电压输出端输出比较电压；充电单元用于为比较电压输出端充电；放电单元连接接地端。本发明实施例中的充放电电路中，在充电过程中，即使电源端中出现噪声，由于时钟信号是接入在放电单元中，充放电电路充放电时间保持不变，当充放电电路应用与振荡器时，可以保持振荡器输出的时钟周期不变；从而避免或降低振荡电路输出时钟的周期和占空比的波动。 【EN】The embodiment of the invention provides a charge and discharge circuit and an oscillator, wherein the charge and discharge circuit comprises: a reference voltage generating unit, a charging unit, and a discharging unit; the reference voltage generating unit is used for outputting the reference voltage through a reference voltage output end after the reference voltage generating unit generates the reference voltage; the discharging unit is used for outputting comparison voltage at a comparison voltage output end according to the clock signal received by the clock input end; the charging unit is used for charging the comparison voltage output end; the discharge unit is connected with the grounding terminal. In the charging and discharging circuit in the embodiment of the invention, in the charging process, even if noise occurs in a power supply end, as the clock signal is connected into the discharging unit, the charging and discharging time of the charging and discharging circuit is kept unchanged, and when the charging and discharging circuit is applied to an oscillator, the clock period output by the oscillator can be kept unchanged; thereby avoiding or reducing fluctuations in the period and duty cycle of the oscillator circuit output clock.

摘要：【中文】本发明实施例提供了一种充放电电路及振荡器，该充放电电路包括：参考电压产生单元、充电单元、放电单元；参考电压产生单元用于在参考电压产生单元产生参考电压后，通过参考电压输出端输出；放电单元用于根据时钟输入端接收到的时钟信号，在比较电压输出端输出比较电压；充电单元用于为比较电压输出端充电；放电单元包括：第一N型晶体管、第二N型晶体管、第三N型晶体管。本发明实施例中的充放电电路中，在充电过程中，即使电源端中出现噪声，由于时钟信号是接入在放电单元中，充放电电路充放电时间保持不变，当充放电电路应用与振荡器时，可以保持振荡器输出的时钟周期不变；从而避免或降低振荡电路输出时钟的周期和占空比的波动。 【EN】The embodiment of the invention provides a charge and discharge circuit and an oscillator, wherein the charge and discharge circuit comprises: a reference voltage generating unit, a charging unit, and a discharging unit; the reference voltage generating unit is used for outputting the reference voltage through a reference voltage output end after the reference voltage generating unit generates the reference voltage; the discharging unit is used for outputting comparison voltage at a comparison voltage output end according to the clock signal received by the clock input end; the charging unit is used for charging the comparison voltage output end; the discharge unit includes: a first N-type transistor, a second N-type transistor, and a third N-type transistor. In the charging and discharging circuit in the embodiment of the invention, in the charging process, even if noise occurs in a power supply end, as the clock signal is connected into the discharging unit, the charging and discharging time of the charging and discharging circuit is kept unchanged, and when the charging and discharging circuit is applied to an oscillator, the clock period output by the oscillator can be kept unchanged; thereby avoiding or reducing fluctuations in the period and duty cycle of the oscillator circuit output clock.

摘要：【中文】本发明实施例提供了一种灵敏放大器电路，该包括：第一输入端为灵敏放大器电路的基带基准电压输入端；第二输入端与第一N型场效应管单元的源端连接；第一N型场效应管单元的栅端与第一N型场效应管单元的漏端连接，并与第一P型场效应管单元的漏端、嵌位电压输出端连接；第一P型场效应管单元的栅端与运放输出端连接；第一P型场效应管单元的源端与电源端连接；第一N型场效应管单元的源端与电阻的一端连接；电阻的另一端与接地端连接。本发明实施例，第一P型场效应管单元的漏端有很强的驱动能力即使非易失存储器中需要多个灵敏放大器，也只需要共用一个上述灵敏放大器电路进行统一嵌位，因此，灵敏放大器总体的面积和功耗可以大大减少。 【EN】An embodiment of the present invention provides a sense amplifier circuit, including: the first input end is a baseband reference voltage input end of the sensitive amplifier circuit; the second input end is connected with the source end of the first N-type field effect transistor unit; the grid end of the first N-type field effect transistor unit is connected with the drain end of the first N-type field effect transistor unit, and is connected with the drain end of the first P-type field effect transistor unit and the clamping voltage output end; the grid end of the first P-type field effect transistor unit is connected with the output end of the operational amplifier; the source end of the first P-type field effect transistor unit is connected with the power supply end; the source end of the first N-type field effect transistor unit is connected with one end of the resistor; the other end of the resistor is connected with the grounding end. In the embodiment of the invention, the drain terminal of the first P-type field effect transistor unit has strong driving capability, even though a plurality of sensitive amplifiers are needed in the nonvolatile memory, only one sensitive amplifier circuit needs to be shared for carrying out unified clamping, so that the total area and power consumption of the sensitive amplifiers can be greatly reduced.

摘要：【中文】本发明实施例提供了一种电荷泵系统及非易失存储器，该系统包括：包括了比较单元、振荡器单元、锁存单元、电荷泵单元、第一电阻、第二电阻；比较单元包括第一输入接口、第二输入接口、第一输出接口；第一输入接口用于接入参考电压；第一输出接口与振荡器单元的输入端、及锁存单元的使能端连接；振荡器单元的输出端与锁存单元的输入端连接；锁存单元的输出端与电荷泵单元的输入端连接。本发明实施例中，在振荡器单元输出端设置了锁存单元，当比较单元的输出端拉低时，锁存单元可以将时钟信号锁存在比较单元的输出端下降沿出现前的状态，因此能有效避免电荷泵系统中的毛刺，避免电荷泵单元内部节点出错。 【EN】The embodiment of the invention provides a charge pump system and a nonvolatile memory, wherein the system comprises: the circuit comprises a comparison unit, an oscillator unit, a latch unit, a charge pump unit, a first resistor and a second resistor; the comparison unit comprises a first input interface, a second input interface and a first output interface; the first input interface is used for accessing a reference voltage; the first output interface is connected with the input end of the oscillator unit and the enabling end of the latch unit; the output end of the oscillator unit is connected with the input end of the latch unit; the output end of the latch unit is connected with the input end of the charge pump unit. In the embodiment of the invention, the output end of the oscillator unit is provided with the latch unit, and when the output end of the comparison unit is pulled down, the latch unit can latch the clock signal in a state before the falling edge of the output end of the comparison unit appears, so that the burr in the charge pump system can be effectively avoided, and the error of the internal node of the charge pump unit is avoided.

摘要：【中文】本发明实施例提供了一种电荷泵系统及非易失存储器，该系统包括：包括了振荡器单元、电荷泵单元；振荡器单元的输出端与电荷泵单元的输入端连接，用于通过振荡器单元的输出端的输出信号，控制电荷泵单元进行冲压；振荡器单元包括：延时反相电路、锁存器；锁存器包括：第一输入接口、第二输入接口和第一输出接口；延时反相电路的输出端与第一输入接口连接；第一输出接口与电荷泵单元的输入端连接；第二输入接口作为所述振荡器单元的输入端，用于接收使能信号。本发明实施例在振荡器单元中设置了锁存器，当使能信号拉低时，锁存器可以将时钟信号锁存在使能信号下降沿出现前的状态，因此能有效避免电荷泵系统中的毛刺，避免电荷泵单元出现过冲。 【EN】The embodiment of the invention provides a charge pump system and a nonvolatile memory, wherein the system comprises: the device comprises an oscillator unit and a charge pump unit; the output end of the oscillator unit is connected with the input end of the charge pump unit and is used for controlling the charge pump unit to punch through an output signal of the output end of the oscillator unit; the oscillator unit includes: a delay inverting circuit, a latch; the latch includes: a first input interface, a second input interface and a first output interface; the output end of the delay inverting circuit is connected with the first input interface; the first output interface is connected with the input end of the charge pump unit; the second input interface is used as an input end of the oscillator unit and used for receiving an enabling signal. The embodiment of the invention arranges the latch in the oscillator unit, when the enable signal is pulled down, the latch can latch the clock signal in a state before the falling edge of the enable signal appears, thereby effectively avoiding the burr in the charge pump system and avoiding the overshoot of the charge pump unit.