摘要：【中文】本发明提供一种分栅快闪存储器的制造方法，包括：提供一衬底，所述衬底上形成有衬底氧化层及结构层，所述结构层中形成有第一沟槽，其中，所述结构层包括：依次堆叠的浮栅层、ONO介质层、控制栅层及第一氮化硅层；在所述第一沟槽中填充字线；对所述字线进行锗离子注入以在所述字线表面形成一非晶层；以及在所述非晶层上形成字线氧化层。通过对所述字线进行锗离子注入可以使得所述字线表面形成一非晶层，所述非晶层有利于所述字线的氧化并能够使得所述字线上生长出厚度均匀的字线氧化层，避免了在后续刻蚀控制栅及浮栅的过程中所述字线氧化层破损而造成所述字线损坏的情况，提高了产品的良率。 【EN】The invention provides a manufacturing method of a split-gate flash memory, which comprises the following steps: providing a substrate, wherein a substrate oxide layer and a structural layer are formed on the substrate, a first groove is formed in the structural layer, and the structural layer comprises: the floating gate layer, the ONO dielectric layer, the control gate layer and the first silicon nitride layer are stacked in sequence; filling word lines in the first grooves; carrying out germanium ion implantation on the word line to form an amorphous layer on the surface of the word line; and forming a word line oxide layer on the amorphous layer. The word line is implanted with germanium ions to form an amorphous layer on the surface of the word line, the amorphous layer is beneficial to oxidation of the word line and enables a word line oxide layer with uniform thickness to grow on the word line, the situation that the word line is damaged due to damage of the word line oxide layer in the subsequent process of etching a control gate and a floating gate is avoided, and the yield of products is improved.

摘要：【中文】一种CMOS射频开关的仿真方法、装置及通信终端。所述方法包括：接收第一值；基于所述第一值，获得第一函数的当前值；所述第一函数以所述CMOS射频开关施加的栅极电压值为自变量的函数，且在所述CMOS射频开关处于开态时，所述第一函数的值为第一函数值，在所述CMOS射频开关处于关态时，所述第一函数的值为第二函数值；所述第一函数值小于第二函数值；接收第二值；接收第三值；基于所述第二值及第三值，输出所述CMOS射频开关的关态电容值；基于所述第二值、第三值及所述第一函数的当前值，输出所述CMOS射频开关的开态电阻值。采用上述方案，可以提高基于SOI工艺的CMOS射频开关的仿真速度。 【EN】A simulation method and device for a CMOS radio frequency switch and a communication terminal are provided. The method comprises the following steps: receiving a first value; obtaining a current value of a first function based on the first value; the first function takes a gate voltage value applied by the CMOS radio frequency switch as an independent variable function, the value of the first function is a first function value when the CMOS radio frequency switch is in an on state, and the value of the first function is a second function value when the CMOS radio frequency switch is in an off state; the first function value is smaller than the second function value; receiving a second value; receiving a third value; outputting an off-state capacitance value of the CMOS radio frequency switch based on the second value and the third value; and outputting the on-state resistance value of the CMOS radio frequency switch based on the second value, the third value and the current value of the first function. By adopting the scheme, the simulation speed of the CMOS radio frequency switch based on the SOI process can be improved.

摘要：【中文】本发明公开了一种改善掺杂非晶硅薄膜方块电阻面内均一性的方法，其特征在于：在淀积掺杂非晶硅薄膜时，在参与反应的气体中通入锗烷。淀积时，淀积温度300～450摄氏度，压力1～10Torr，高频功率100～1000w,低频功率100～1000w,硅烷流量100～1000sccm，淀积时间10～100s，Ar流量500～5000sccm。锗烷流量为10～1000sccm，淀积时间10～100s。本发明在通入了一定量的锗烷后，由于Ge和B的结合能力与硅不同从而改变了掺杂的分布，改善了面内均一性。 【EN】The invention discloses a method for improving the in-plane uniformity of a square resistor of a doped amorphous silicon film, which is characterized by comprising the following steps of: when the doped amorphous silicon thin film is deposited, germane is introduced into the gas participating in the reaction. During deposition, the deposition temperature is 300-450 ℃, the pressure is 1-10 Torr, the high-frequency power is 100-1000 w, the low-frequency power is 100-1000 w, the silane flow is 100-1000 sccm, the deposition time is 10-100 s, and the Ar flow is 500-5000 sccm. The germane flow is 10-1000 sccm, and the deposition time is 10-100 s. After a certain amount of germane is introduced, the doping distribution is changed and the in-plane uniformity is improved due to the fact that the combination capacity of Ge and B is different from that of silicon.

摘要：【中文】本发明提供的一种金属硅化物的形成方法，包括以下步骤：提供一半导体衬底，半导体衬底上形成有天然氧化膜；刻蚀去除天然氧化膜，并刻蚀停止在半导体衬底上，刻蚀时间为刻蚀了厚度c的天然氧化膜所需要的时间，厚度c满足公式：c＝a+b，其中，a为天然氧化膜的膜厚，b为变量；在半导体衬底上形成金属膜层和添加剂膜层，并执行第一次热退火工艺，以形成初始金属硅化物；去除未形成初始金属硅化物的金属膜层和添加剂膜层；以及执行第二次热退火工艺。本发明通过调整刻蚀去除天然氧化膜的时间，来降低刻蚀中形成的不连续的硅化物缺陷的数量，以提高金属硅化物的电阻均一性，从而提高后续所形成器件的品质，还可以调整形成金属硅化物所在区域的阻值。 【EN】The invention provides a method for forming metal silicide, which comprises the following steps: providing a semiconductor substrate, wherein a natural oxide film is formed on the semiconductor substrate; and etching to remove the natural oxide film, and stopping etching on the semiconductor substrate, wherein the etching time is the time required by etching the natural oxide film with the thickness c, and the thickness c meets the formula: c is a + b, wherein a is the thickness of the natural oxide film, and b is variable; forming a metal film layer and an additive film layer on a semiconductor substrate, and performing a first thermal annealing process to form an initial metal silicide; removing the metal film layer and the additive film layer which are not formed with the initial metal silicide; and performing a second thermal annealing process. The invention reduces the number of discontinuous silicide defects formed in etching by adjusting the time for removing the natural oxide film in etching, so as to improve the resistance uniformity of the metal silicide, thereby improving the quality of a subsequent formed device, and also adjusting the resistance value of an area where the formed metal silicide is positioned.

摘要：【中文】本发明通过在所述半导体衬底上形成图形化的掩模层，所述图形化的掩模层覆盖了部分的所述存储区，并在所述字线栅极沿其延伸方向的端面上暴露出部分长度的字线栅极，所述图形化的掩模层还覆盖了所述逻辑区用于形成逻辑栅极的区域，使得在刻蚀形成逻辑栅极时，字线栅极端面上的部分长度的共享字线被刻蚀掉，避免共享字线和控制栅极之间在存储器边缘因隔离氮化硅缺失导致的短路问题，从而避免了分栅快闪存储器的失效问题。 【EN】According to the invention, the patterned mask layer is formed on the semiconductor substrate, the patterned mask layer covers part of the storage region, the word line grid with partial length is exposed on the end face of the word line grid along the extension direction of the word line grid, and the patterned mask layer also covers the region of the logic region for forming the logic grid, so that when the logic grid is formed by etching, the shared word line with partial length on the end face of the word line grid is etched, the short circuit problem caused by the lack of isolation silicon nitride at the edge of the memory between the shared word line and the control grid is avoided, and the failure problem of the split-grid flash memory is avoided.

摘要：【中文】本发明提供了一种形成导电互连线的方法，包括：提供一衬底，所述衬底上形成有导电层；刻蚀所述导电层以得到导电互连线；对形成有所述导电互连线的半导体器件执行湿法清洗工艺；执行烘烤工艺以及执行氧化工艺。在本发明中，执行湿法清洗工艺之后，增加烘烤工艺和氧化工艺，其中，所述烘烤工艺可以去除湿法清洗工艺后所述导电互连线表面的水汽，所述氧化工艺可以使得所述导电互连线的表面生长出致密的氧化膜，避免了所述导电互连线与残留的刻蚀副产物发生反应的情况，从而避免了导电互连线的腐蚀缺陷的情况，提高了产品的良率和产品的可靠性。 【EN】The invention provides a method for forming a conductive interconnection line, which comprises the following steps: providing a substrate, wherein a conducting layer is formed on the substrate; etching the conductive layer to obtain a conductive interconnection line; performing a wet cleaning process on the semiconductor device on which the conductive interconnection line is formed; a baking process is performed and an oxidation process is performed. According to the invention, after the wet cleaning process is executed, a baking process and an oxidation process are added, wherein the baking process can remove water vapor on the surface of the conductive interconnection line after the wet cleaning process, and the oxidation process can enable a compact oxidation film to grow on the surface of the conductive interconnection line, so that the condition that the conductive interconnection line reacts with residual etching byproducts is avoided, the condition of corrosion defects of the conductive interconnection line is avoided, and the yield of products and the reliability of the products are improved.

摘要：【中文】本发明公开了一种沟槽型功率MOSFET,在一半导体基片中具有多个第一沟槽，所述的多个第一沟槽内填充有第一介质层；所述第一介质层中再形成3个第二沟槽，所述第二沟槽包括位于中间的源控制栅沟槽以及位于源控制栅两侧的多晶硅栅沟槽，所述源控制栅的沟槽深度大于多晶硅栅的沟槽深度；所述源控制栅的沟槽与多晶硅栅的沟槽中还具有第二介质层，所述第二介质层附着于所述各沟槽的内侧壁及底部；所述的源控制栅沟槽以及多晶硅栅沟槽中均填充满多晶硅。本发明通过在源控制栅与多晶硅栅之间增加第二介质层，使得源控制栅与多晶硅栅之间不再受限于栅介质层的厚度，有效改善了源控制栅与多晶硅栅之间由于间隔过小而导致的漏电。 【EN】The invention discloses a groove type power MOSFET, which is characterized in that a semiconductor substrate is provided with a plurality of first grooves, and a first dielectric layer is filled in the first grooves; forming 3 second grooves in the first dielectric layer, wherein the second grooves comprise a source control gate groove in the middle and polysilicon gate grooves on two sides of the source control gate, and the depth of the source control gate groove is greater than that of the polysilicon gate groove; second dielectric layers are arranged in the grooves of the source control grid and the grooves of the polysilicon grid, and the second dielectric layers are attached to the inner side walls and the bottoms of the grooves; and the source control gate trench and the polysilicon gate trench are filled with polysilicon. According to the invention, the second dielectric layer is added between the source control gate and the polysilicon gate, so that the thickness of the gate dielectric layer is not limited between the source control gate and the polysilicon gate, and the electric leakage caused by the undersize interval between the source control gate and the polysilicon gate is effectively improved.

摘要：【中文】本发明提供一种半导体器件及其制造方法，该制造方法包括：提供衬底；在所述衬底上依次形成有第一介质层、浮栅、第二介质层和控制栅，以及形成于所述浮栅、第二介质层和控制栅侧壁的间隔氧化层，所述第一介质层为氧化层；沿字线区域湿法蚀刻间隔氧化层和第一介质层，以减薄第一介质层形成隧穿氧化层，以及减薄间隔氧化层形成侧壁氧化层，以使控制栅转角处的侧壁氧化层与隧穿氧化层的厚度比为125％至145％。本发明能够提高半导体器件的控制栅与字线之间抗压能力，能够使半导体器件的擦除性能更加稳定、擦除效果更好，能够提高半导体器件的质量。 【EN】The invention provides a semiconductor device and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a substrate; a first dielectric layer, a floating gate, a second dielectric layer, a control gate and an interval oxide layer formed on the side walls of the floating gate, the second dielectric layer and the control gate are sequentially formed on the substrate, wherein the first dielectric layer is an oxide layer; and etching the interval oxide layer and the first dielectric layer along the word line region by a wet method to thin the first dielectric layer to form a tunneling oxide layer, and thinning the interval oxide layer to form a side wall oxide layer, so that the thickness ratio of the side wall oxide layer at the corner of the control gate to the tunneling oxide layer is 125-145%. The invention can improve the pressure resistance between the control gate and the word line of the semiconductor device, can make the erasing performance of the semiconductor device more stable and the erasing effect better, and can improve the quality of the semiconductor device.

摘要：【中文】本申请涉及一种半导体集成电路器件，具体涉及一种静电释放(Electro Static Discharge，ESD)保护的栅极接地NMOS管结构。ESD保护的栅极接地MOS结构，包括第一导电类型阱区和第二导电类型阱区，第二导电类型阱区环绕在第一导电类型阱区外侧；第一导电类型阱区中形成第二导电类型扩散区，和环绕第二导电类型扩散区的第一导电类型阱环区；第二导电类型扩散区中形成多个第二导电类型注入区，多个第二导电类型注入区间隔排布，相邻两个第二导电类型注入区的间隔上形成栅极，栅极接地；第二导电类型阱区中设有第二导电类型注入区。通过多指状MOS管和双层保护环能够对输入输出端和电源端同时进行静电保护。 【EN】The present disclosure relates to a semiconductor integrated circuit device, and more particularly, to a grounded-gate NMOS structure for electrostatic Discharge (ESD) protection. The grid grounding MOS structure for ESD protection comprises a first conductive type well region and a second conductive type well region, wherein the second conductive type well region surrounds the outer side of the first conductive type well region; a second conductive type diffusion region and a first conductive type well ring region surrounding the second conductive type diffusion region are formed in the first conductive type well region; a plurality of second conductive type injection regions are formed in the second conductive type diffusion region, the plurality of second conductive type injection regions are arranged at intervals, a grid electrode is formed at the interval of two adjacent second conductive type injection regions, and the grid electrode is grounded; the second conductive type well region is provided with a second conductive type injection region. The input and output ends and the power supply end can be simultaneously subjected to electrostatic protection through the multi-finger MOS tube and the double-layer protection ring.

摘要：【中文】本发明公开了一种MEMS桥梁柱结构及形成方法，所述结构采用多层薄膜复合结构，主要包括第一氧化硅层、第二氧化硅层、第三氧化硅层、非晶硅层、钛/氮化钛层以及ONO层；所述的衬底中包含有电连接层。本发明所述的MEMS桥梁柱结构及形成方法，通过将不同的模层结构组合，得到一种适用于MEMS产品中桥梁柱的结构应用，可以有效的支撑整个悬空MEMS结构，降低梁柱倒塌风险，同时不影响桥梁柱的导通性能。 【EN】The invention discloses an MEMS bridge column structure and a forming method thereof, wherein the structure adopts a multilayer film composite structure and mainly comprises a first silicon oxide layer, a second silicon oxide layer, a third silicon oxide layer, an amorphous silicon layer, a titanium/titanium nitride layer and an ONO layer; the substrate comprises an electrical connection layer. According to the MEMS bridge-column structure and the forming method, different mould layer structures are combined to obtain the structural application of the bridge column in the MEMS product, the whole suspended MEMS structure can be effectively supported, the risk of collapse of the bridge column is reduced, and meanwhile the conduction performance of the bridge column is not influenced.