摘要：本发明公开了一种在内存中实现带有正负数乘加的SRAM电路，通过将多个乘数存入一列单元中，多个被乘数通过SRAM的字线WL输入，与单元内的相应的乘数进行乘法运算，再将每组乘得的结果累加在位线上，可直接通过位线电压得出乘加的结果。另外添加了一列参考列以判断计算结果是正数还是负数，以实现正负数的乘法。

摘要：【中文】本发明公开了一种用于二值神经网络的双字线6TSRAM单元电路，其中：PMOS晶体管M1和M2为预充电管，M1和M2的源极共同接到电源V_dd，M1的漏级接在位线BLB上，M2的漏级接在位线BL上；且M1和M2的栅极共同连接到控制端sw2；PMOS晶体管M3为一列6TSRAM单元阵列共用的平衡电压管，M3的源级、漏级分别与位线BLB、BL相连接，用于平衡两条位线BL和BLB上面的电压；且M3的栅极连接到控制端sw1；电容C0和C1为位线BLB和BL上的寄生电容。该电路结构减少了面积和功耗，改善了线性度，同时将模拟域的运算与数字域的运算相结合，减少了模拟域的计算量与电路的复杂性。 【EN】The invention discloses a double-word line 6TSRAM unit circuit for a binary neural network, wherein: PMOS transistors M1 and M2 are pre-charge transistors, and the sources of M1 and M2 are commonly connected to power supply V_ddThe drain of M1 is connected to bit line BLB, and the drain of M2 is connected to bit line BL; and the gates of M1 and M2 are commonly connected to control terminal sw 2; the PMOS transistor M3 is a balancing voltage tube shared by a column of 6TSRAM cell arrays, and the source and drain of M3 are respectively connected with the bit lines BLB and BL and used for balancing the voltages on the two bit lines BL and BLB; and the gate of M3 is connected to control terminal sw 1; capacitances C0 and C1 are parasitic capacitances on bit lines BLB and BL. The circuit structure reduces the area and power consumption, improves the linearity, and simultaneously combines the operation of an analog domain and the operation of a digital domain, thereby reducing the calculation amount of the analog domain and the complexity of the circuit.

摘要：【中文】本发明公开了一种RHPD‑12T抗辐照SRAM存储单元电路，包括十个NMOS晶体管和两个PMOS晶体管，内围节点由PMOS晶体管P1和P2交叉耦合，NMOS晶体管N3和N4作为下拉管；外围节点由NMOS晶体管N5和N6交叉耦合，NMOS晶体管N1与N2作为上拉管；外围存储节点S0和S1通过控制NMOS晶体管N3和N4对内围存储节点Q和QB进行加固；内外围的四个存储节点Q、QB、S0、S1通过四个NMOS晶体管N7～N10连接到两条位线BL和BLN，四个NMOS晶体管N7～N10的开启由字线WL控制。该电路能够在牺牲较小单元面积的情况下大幅度提高存储单元的速度，降低存储单元的功耗。 【EN】The invention discloses an RHPD-12T radiation-resistant SRAM memory cell circuit, which comprises ten NMOS transistors and two PMOS transistors, wherein inner peripheral nodes are cross-coupled by the PMOS transistors P1 and P2, and the NMOS transistors N3 and N4 are used as pull-down tubes; the peripheral nodes are cross-coupled by NMOS transistors N5 and N6, and the NMOS transistors N1 and N2 are used as pull-up tubes; the peripheral storage nodes S0 and S1 reinforce the peripheral storage nodes Q and QB by controlling the NMOS transistors N3 and N4; the four storage nodes Q, QB, S0, S1 of the inner and outer peripheries are connected to two bit lines BL and BLN through four NMOS transistors N7 to N10, and the turn-on of the four NMOS transistors N7 to N10 is controlled by a word line WL. The circuit can greatly improve the speed of the memory unit and reduce the power consumption of the memory unit under the condition of sacrificing smaller unit area.

摘要：本发明公开了一种用于提高内存内计算线性度和一致性的电路，包括具有双字线的6T SRAM存储阵列、字线控制模块、模式选择模块、时序控制模块、预充模块、电流镜模块、开关模块和缓冲器模块，6T SRAM存储阵列分别与所述预充模块、字线控制模块、缓冲器模块相连接；时序控制模块分别与所述预充模块、开关模块、电流镜模块相连接；电流镜模块与所述缓冲器模块相连接；利用电流镜模块将位线BL上的电压进行钳位，阻止位线BL上的电压降低并镜像单元的读取电流，最后转换为电压再通过所述缓冲器模块输出作为最终的计算结果。上述电路能够实现高线性度和高一致性的内存内计算，从而极大提高了内存内计算的实用性。

摘要：【中文】本发明公开了一种频率可调的基于RC的环形振荡器电路，包括电压跟随器、6‑BIT电容阵列、电阻R1和R2、六个反相器，电压跟随器包括两个NMOS晶体管N6和N7、二极管D1、滤波电容C7和电阻R0，该电压跟随器与反相器阵列的VDD相连；六个反相器组成反相器阵列；6‑BIT电容阵列和电阻R1、R2串联形成RC网络，电阻R1的左端N点经过三个串联的反相器INV1、INV2、INV3到6‑BIT电容阵列左端G点形成一个回路，电阻R2和6‑BIT电容阵列的公共端M点经过另外三个串联的反相器INV4、INV5、INV0到电阻R1的左端N点形成另一个回路。该电路采用反相器构成环形电路，功耗极低且面积很小。 【EN】The invention discloses a frequency-adjustable ring oscillator circuit based on RC, which comprises a voltage follower, a 6-BIT capacitor array, resistors R1 and R2 and six inverters, wherein the voltage follower comprises two NMOS transistors N6 and N7, a diode D1, a filter capacitor C7 and a resistor R0, and is connected with VDD of the inverter array; six inverters form an inverter array; the 6-BIT capacitor array and the resistors R1 and R2 are connected in series to form an RC network, a point N at the left end of the resistor R1 forms a loop through three inverters INV1, INV2 and INV3 which are connected in series to a point G at the left end of the 6-BIT capacitor array, and a point M at the common end of the resistor R2 and the 6-BIT capacitor array forms another loop through the other three inverters INV4, INV5 and INV0 which are connected in series to a point N at the left end of the resistor R1. The circuit adopts the phase inverter to form a ring circuit, and has extremely low power consumption and small area.