摘要：【中文】本发明实施例提供了一种灵敏放大器电路，该包括：第一输入端为灵敏放大器电路的基带基准电压输入端；第二输入端与第一N型场效应管单元的源端连接；第一N型场效应管单元的栅端与第一N型场效应管单元的漏端连接，并与第一P型场效应管单元的漏端、嵌位电压输出端连接；第一P型场效应管单元的栅端与运放输出端连接；第一P型场效应管单元的源端与电源端连接；第一N型场效应管单元的源端与电阻的一端连接；电阻的另一端与接地端连接。本发明实施例，第一P型场效应管单元的漏端有很强的驱动能力即使非易失存储器中需要多个灵敏放大器，也只需要共用一个上述灵敏放大器电路进行统一嵌位，因此，灵敏放大器总体的面积和功耗可以大大减少。 【EN】An embodiment of the present invention provides a sense amplifier circuit, including: the first input end is a baseband reference voltage input end of the sensitive amplifier circuit; the second input end is connected with the source end of the first N-type field effect transistor unit; the grid end of the first N-type field effect transistor unit is connected with the drain end of the first N-type field effect transistor unit, and is connected with the drain end of the first P-type field effect transistor unit and the clamping voltage output end; the grid end of the first P-type field effect transistor unit is connected with the output end of the operational amplifier; the source end of the first P-type field effect transistor unit is connected with the power supply end; the source end of the first N-type field effect transistor unit is connected with one end of the resistor; the other end of the resistor is connected with the grounding end. In the embodiment of the invention, the drain terminal of the first P-type field effect transistor unit has strong driving capability, even though a plurality of sensitive amplifiers are needed in the nonvolatile memory, only one sensitive amplifier circuit needs to be shared for carrying out unified clamping, so that the total area and power consumption of the sensitive amplifiers can be greatly reduced.

摘要：【中文】本发明实施例提供了一种存储器控制电路、方法及非易失存储器，该电路包括：电压检测模块与电源接入端连接，用于在电源接入端接入电源时，根据电源的电压值输出控制信号；控制模块与第一开关、第二开关、第三开关、电压检测模块通信连接，用于根据电压检测模块输出的控制信号，控制第一开关、第二开关、第三开关的开合状态。本发明实施例中，控制模块根据控制信号通过控制第一开关、第二开关、第三开关的开合状态，控制第一电荷泵模块、第二电荷泵模块的在电路中的接入情况，从而通过第一电荷泵模块、第二电荷泵模块的不同接入情况，实现对接入电源不同程度的抬高，使得在不同的接入电源中都能得到存储器需要的电压值。 【EN】The embodiment of the invention provides a memory control circuit, a memory control method and a nonvolatile memory, wherein the circuit comprises: the voltage detection module is connected with the power supply access end and used for outputting a control signal according to the voltage value of the power supply when the power supply access end is connected with the power supply; the control module is in communication connection with the first switch, the second switch, the third switch and the voltage detection module and is used for controlling the opening and closing states of the first switch, the second switch and the third switch according to the control signal output by the voltage detection module. In the embodiment of the invention, the control module controls the access conditions of the first charge pump module and the second charge pump module in the circuit by controlling the opening and closing states of the first switch, the second switch and the third switch according to the control signal, so that the access power supply is lifted to different degrees by different access conditions of the first charge pump module and the second charge pump module, and the voltage values required by the memory can be obtained in different access power supplies.

摘要：【中文】本发明实施例提供了一种振荡器电路及非易失存储器，电路包括了延时反相单元、选择锁存单元、与非门单元、非门单元、P型场效应管：P10。本发明实施例中，通过选择锁存单元将与非门单元的第三输出端的信号和非门单元的输出端的信号，经过选择和锁存处理后，使得当EN出现下降沿时，选择锁存单元可以将第二输出端的输出信号锁存在下降沿出现前的状态，因此能有效避免时钟电路中的毛刺，输出完整无毛刺的时钟信号。 【EN】The embodiment of the invention provides an oscillator circuit and a nonvolatile memory, wherein the circuit comprises a time delay inverting unit, a selection latch unit, a NAND gate unit, a NOT gate unit and a P-type field effect transistor: p10. In the embodiment of the invention, after the selection and latch unit selects and latches the signal of the third output end of the NAND gate unit and the signal of the output end of the NOT gate unit, when EN has a falling edge, the selection latch unit can latch the output signal of the second output end in a state before the falling edge occurs, so that the glitch in the clock circuit can be effectively avoided, and a complete glitch-free clock signal is output.