摘要：【中文】本发明公开了一种小型断路器操作机构,包括断路器的外壳、手柄、活动触头和固定触头，所述外壳通过转轴与手柄的连接端转动连接，所述手柄的手持端位于外壳的外部，且连接端插入外壳内部固定连接驱动盘，且连接点位于圆心上，所述驱动盘的对侧固定安装偏心柱，所述偏心柱，所述偏心柱的端部活动安装连杆A，所述连杆A的另一端活动连接连杆B，所述连杆B活动连接连接件，所述连接件固定连接推动块，本发明的有益效果是：结构简单，便于使用，不仅如此还方便观察操作机构内部具体情况，发现问题所在；可以避免因为晃动而导致操作机构出现错误性自动开合闸的情况发生，增加了安全性。 【EN】The invention discloses a small-sized circuit breaker operating mechanism, which comprises a shell of a circuit breaker, a handle, a movable contact and a fixed contact, wherein the shell is rotatably connected with a connecting end of the handle through a rotating shaft, a handheld end of the handle is positioned outside the shell, the connecting end is inserted into the shell and fixedly connected with a driving disc, a connecting point is positioned on a circle center, an eccentric column is fixedly arranged on the opposite side of the driving disc, a connecting rod A is movably arranged at the end part of the eccentric column, the other end of the connecting rod A is movably connected with a connecting rod B, the connecting rod B is movably connected with a connecting piece, and the connecting piece is fixedly connected with a pushing block. The structure is simple, the use is convenient, the specific conditions in the operating mechanism can be conveniently observed, and the problems can be found; the situation that the operating mechanism is mistakenly and automatically switched on and switched off due to shaking can be avoided, and the safety is improved.

摘要：【中文】本发明公开了一种断路器触头系统,包括灭弧筒、动触头和静触头，所述动触头和静触头均位于灭弧筒内腔，所述灭弧筒的内壁底部螺纹连接底板，所述底板的底部固定安装电机，所述电机的动力输出端固定连接转轴，转轴贯穿底板并延伸至灭弧筒的内腔，转轴的顶部上下活动连接按压杆，所述按压杆的侧壁对称安装动触头，按压杆的顶部贯穿灭弧筒并延伸至灭弧筒的顶部外侧并固定连接旋钮，所述底板的顶部固定安装有固定板，所述固定板通过触动弹簧固定连接静触头，本发明的有益效果是：具有保护措施，安全性高；连接紧密，不受触头的厚度和弹性影响；使用寿命长。 【EN】The invention discloses a circuit breaker contact system, which comprises an arc extinguishing cylinder, a moving contact and a static contact, wherein the moving contact and the static contact are both positioned in an inner cavity of the arc extinguishing cylinder, the bottom of the inner wall of the arc extinguishing cylinder is in threaded connection with a bottom plate, a motor is fixedly installed at the bottom of the bottom plate, a power output end of the motor is fixedly connected with a rotating shaft, the rotating shaft penetrates through the bottom plate and extends to the inner cavity of the arc extinguishing cylinder, the top of the rotating shaft is movably connected with a pressing rod up and down, the moving contact is symmetrically installed on the side wall of the pressing rod, the top of the pressing rod penetrates through the arc extinguishing cylinder and extends to the outer side of the top of the arc extinguishing cylinder and is fixedly connected with a knob, a fixing plate is fixedly: the safety is high due to protection measures; the connection is tight and is not influenced by the thickness and the elasticity of the contact; the service life is long.

摘要：【中文】本发明公开了一种基于AXI‑ST接口访问FPGA存储单元的方法、设备和存储介质，方法包括以下步骤：开启AXI‑ST接口的从模式以接收CPU发送的读写操作帧，对读写操作帧进行解析并基于解析结果生成控制信号；判断控制信号是否为读请求信号；响应于控制信号为读请求信号，基于AXI‑MM接口读取FPGA存储单元的数据；以及基于数据组成AXI‑ST接口的读响应帧，并开启AXI‑ST接口的主模式以将读响应帧发送到CPU。本发明提出的基于AXI‑ST接口访问FPGA存储单元的方法、设备及介质通过将AXI‑MM接口的读写指令封装在AXI‑ST接口的帧中进行传输的方式，可以不用进行接口的转换即可实现控制。 【EN】The invention discloses a method, equipment and a storage medium for accessing an FPGA storage unit based on an AXI-ST interface, wherein the method comprises the following steps: opening a slave mode of an AXI-ST interface to receive a read-write operation frame sent by a CPU, analyzing the read-write operation frame and generating a control signal based on an analysis result; judging whether the control signal is a read request signal; reading data of the FPGA storage unit based on the AXI-MM interface in response to the control signal being a read request signal; and composing a read response frame of the AXI-ST interface based on the data, and opening a master mode of the AXI-ST interface to transmit the read response frame to the CPU. The method, the equipment and the medium for accessing the FPGA storage unit based on the AXI-ST interface, which are provided by the invention, can realize control without interface conversion by packaging the read-write instruction of the AXI-MM interface in the frame of the AXI-ST interface for transmission.

摘要：【中文】本发明公开了一种电路逻辑重构系统，本申请中，处理器可以持续地监听电路的异常状态，并在监听到异常状态时通过改写读写寄存器的数值而控制芯片的核心控制模块执行对应的电路修复逻辑，提高了发现问题以及解决问题的速度，不会遗漏瞬间出现的异常状态，且无需工作人员通过调试终端进行操作，节省了人力成本。本发明还公开了一种芯片，具有如上电路逻辑重构系统相同的有益效果。 【EN】The invention discloses a circuit logic reconfiguration system, wherein a processor can continuously monitor the abnormal state of a circuit and controls a core control module of a chip to execute corresponding circuit repair logic by rewriting the numerical value of a read-write register when the abnormal state is monitored, so that the speed of finding and solving problems is improved, the abnormal state which appears instantly can not be omitted, a worker does not need to operate through a debugging terminal, and the labor cost is saved. The invention also discloses a chip which has the same beneficial effects as the circuit logic reconfiguration system.

摘要：【中文】本申请公开了一种FPGA异构加速系统及其同步调度方法、服务器和计算机可读存储介质，FPGA异构加速系统中的管理节点和各个FPGA均设置有共享内存区，并均连接至交换机网络；该方法应用于管理节点，包括：根据系统调度任务更新管理节点内共享内存区中的信息数据；生成数据更新提示信息，以便各个FPGA通过交换机网络读取并根据管理节点内更新后的信息数据，对本地共享内存区的信息数据进行对应的维护操作。本申请没有采用FPGA间的级联结构，而是利用交换机网络进行通信，在管理节点进行数据修改后通知各个FPGA，便捷高效地实现系统内各个FPGA间关键信息的共享与同步，极大降低了网络负载，提高了数据调度的交互效率。 【EN】The application discloses an FPGA heterogeneous acceleration system, a synchronous scheduling method thereof, a server and a computer readable storage medium, wherein a management node and each FPGA in the FPGA heterogeneous acceleration system are provided with a shared memory area and are connected to a switch network; the method is applied to a management node and comprises the following steps: updating information data in a shared memory area in a management node according to a system scheduling task; and generating data updating prompt information so that each FPGA reads the information data through the switch network and carries out corresponding maintenance operation on the information data of the local shared memory area according to the updated information data in the management node. According to the method and the system, a cascade structure among the FPGAs is not adopted, the exchanger network is used for communication, the FPGA is informed after the management node modifies the data, the sharing and synchronization of key information among the FPGAs in the system are conveniently and efficiently realized, the network load is greatly reduced, and the interaction efficiency of data scheduling is improved.

摘要：【中文】本申请提供一种图数据的压缩方法，包括：获取原始图数据并确定原始图数据中每条边的节点对；将节点对中的同一源节点按照预设分组规则分组；每个分组中保留一个源节点；根据每个分组的组类型存入对应的FIFO；对源节点的源节点数据和目的节点的目的节点数据添加标签；对FIFO进行轮询并存储，得到压缩图数据。本申请使得对应目的节点数量不同的源节点采用不同的压缩率，在同一分组内仅保留一个源节点，无需存储重复的源节点。可以支持图数据大规模并行解压缩，大幅增加图数据处理带宽。本申请还提供一种图计算系统的数据压缩系统、计算机可读存储介质和一种数据压缩终端，具有上述有益效果。 【EN】The application provides a method for compressing graph data, which comprises the following steps: acquiring original graph data and determining node pairs of each edge in the original graph data; grouping the same source node in the node pair according to a preset grouping rule; one source node is reserved in each packet; storing the packet into a corresponding FIFO according to the group type of each packet; adding labels to source node data of a source node and destination node data of a destination node; and polling and storing the FIFO to obtain the compression map data. According to the method and the device, the source nodes corresponding to different target nodes in number adopt different compression rates, only one source node is reserved in the same group, and repeated source nodes do not need to be stored. The method can support large-scale parallel decompression of the graph data, and greatly increase the processing bandwidth of the graph data. The application also provides a data compression system of the graph calculation system, a computer readable storage medium and a data compression terminal, which have the beneficial effects.

摘要：【中文】本申请公开了一种图数据并行处理的方法，包括：获取图数据；对图数据中的源地址进行筛选，得到独立源地址；根据独立源地址确定对应的目的地址，并对目的地址进行筛选，得到独立目的地址；根据独立源地址和独立目的地址获取对应的独立源数据和独立目的数据，并对独立源数据和独立目的数据进行并行处理，得到并行处理结果。本申请不需要多个处理单元同时处理，仅需一个处理单元即可完成对图数据的并行处理，极大的降低图数据并行处理过程中的缓存开销及通信开销。本申请同时还提供了一种图数据并行处理的装置、设备及可读存储介质，具有上述有益效果。 【EN】The application discloses a method for parallel processing of graph data, which comprises the following steps: acquiring graph data; screening source addresses in the graph data to obtain independent source addresses; determining a corresponding destination address according to the independent source address, and screening the destination address to obtain an independent destination address; and acquiring corresponding independent source data and independent destination data according to the independent source address and the independent destination address, and performing parallel processing on the independent source data and the independent destination data to obtain a parallel processing result. According to the method and the device, a plurality of processing units are not required to process simultaneously, and the parallel processing of the graph data can be completed only by one processing unit, so that the cache overhead and the communication overhead in the graph data parallel processing process are greatly reduced. The application also provides a device, equipment and a readable storage medium for parallel processing of the graph data, and the beneficial effects are achieved.

摘要：【中文】本发明涉及一种N‑叠氮乙酰‑D‑甘露糖胺衍生物及其制备方法和应用。所述化合物的结构如通式(I)所示，其中，R₁选自为O、S、NH、NMe、‑CH＝CH‑；R₃选自为O、S、NH、NMe；R₂选自为H、F、Cl、Br、I、‑OH、‑NH₂、C_1‑6烷基、C_1‑6烷氧基、‑CO‑C_1‑6烷基、‑CO‑NH‑C_1‑6烷基、‑COOC_1‑6烷基、芳基、芳氧基、杂芳基、杂芳氧基、杂环基、杂环氧基；m选自为1‑4的整数；A选自式(I)所述化合物与硝基还原酶发生催化还原反应之后可自行消除或裂解的基团；表示a键或e键。本发明还提供式(I)所示化合物的制备方法和在检测硝基还原酶中的应用。 【EN】The invention relates to an N-azido acetyl-D-mannosamine derivative, a preparation method and application thereof. The structure of the compound is shown as a general formula (I), wherein R₁Selected from O, S, NH, NMe, -CH ═ CH —; r₃Selected from O, S, NH, NMe; r₂Selected from H, F, Cl, Br, I, -OH, -NH₂、C_1‑6Alkyl radical, C_1‑6Alkoxy, -CO-C_1‑6Alkyl, -CO-NH-C_1‑6Alkyl, -COOC_1‑6Alkyl, aryl, aryloxy, heteroaryl, heteroaryloxy, heterocyclyl, heterocyclyloxy; m is selected from integers of 1-4; a is selected from the compounds of formula (I)A group which can be eliminated or cracked by itself after the object and nitroreductase undergo catalytic reduction reaction;represents an a-key or an e-key. The invention also provides a preparation method of the compound shown in the formula (I) and application of the compound in detection of nitroreductase.

摘要：【中文】本发明涉及涉及N‑叠氮基乙酰‑D‑甘露糖胺衍生物在检测酯酶中的应用。本发明主要涉及如下式(I)所示的N‑叠氮基乙酰‑D‑甘露糖胺衍生物及其制备方法和在检测酯酶中的应用：其中，R₁选自为H、F、Cl、Br、I、‑OH、‑NH₂、‑NO₂、‑N₃、C_1‑6烷基、C_1‑6烷氧基、‑CO‑C_1‑6烷基、‑CO‑NH‑C_1‑6烷基、‑COOC_1‑6烷基、芳基、芳基氧基、杂芳基、杂芳基氧基、杂环基、杂环基氧基；所述芳基、芳基氧基、杂芳基、杂芳基氧基、杂环基、杂环基氧基任选被如下基团取代：F、Cl、Br、I、‑OH、‑NH₂、‑NO₂、‑N₃、C_1‑6烷基、C_1‑6烷氧基；R₂、R₃相同或不同，彼此独立地选自为O、S、NH、NMe；n₁、n₂相同或不同，彼此独立地选自为1‑4的整数；表示a键或e键。 【EN】The invention relates to application of N-azidoacetyl-D-mannosamine derivatives in detecting esterase. The invention mainly relates to an N-azido acetyl-D-mannosamine derivative shown as the following formula (I), a preparation method and application thereof in esterase detection:wherein R is₁Selected from H, F, Cl, Br, I, -OH, -NH₂、‑NO₂、‑N₃、C_1‑6Alkyl radical, C_1‑6Alkoxy, -CO-C_1‑6Alkyl, -CO-NH-C_1‑6Alkyl radical、‑COOC_1‑6Alkyl, aryl, aryloxy, heteroaryl, heteroaryloxy, heterocyclyl, heterocyclyloxy; said aryl, aryloxy, heteroaryl, heteroaryloxy, heterocyclyl, heterocyclyloxy optionally substituted with: F. cl, Br, I, -OH, -NH₂、‑NO₂、‑N₃、C_1‑6Alkyl radical, C_1‑6An alkoxy group; r₂、R₃Identical or different, independently of one another, from the group consisting of O, S, NH, NMe; n is₁、n₂Identical or different, independently of one another, from the group consisting of integers from 1 to 4;represents an a-key or an e-key.

摘要：【中文】本发明公开了一种基于FPGA的图计算数据预处理的方法，包括：将内存地址划分出若干具有不同地址范围的基地址，将基地址写入FPGA中的第一FIFO中；响应于原始边数据输入，判断是否需要新的基地址存储原始边数据；当判断需要，从第一FIFO中取出一个新的基地址并存入到与目的节点范围相对应的第二FIFO中；将原始边数据存入新的基地址中，并对每个目的节点范围内的原始边数据进行标数；当源节点范围相同的数据已经全部输入，将源节点范围的相关信息写入第三FIFO中；当判断第三FIFO不为空，根据目的节点的范围顺序依次从SDRAM中读取原始边数据并输出，并将所使用的基地址存入第一FIFO中。本发明还公开了一种装置、设备和介质。本发明处理速度快，可以根据需要进行灵活配置。 【EN】The invention discloses a graph computation data preprocessing method based on an FPGA (field programmable gate array), which comprises the following steps of: dividing the memory address into a plurality of base addresses with different address ranges, and writing the base addresses into a first FIFO (first in first out) in the FPGA; responding to the input of the original side data, and judging whether a new base address is needed to store the original side data; when the judgment is needed, a new base address is taken out from the first FIFO and stored in a second FIFO corresponding to the range of the destination node; storing the original edge data into a new base address, and carrying out number marking on the original edge data in the range of each destination node; when the data with the same source node range are all input, the related information of the source node range is written into a third FIFO; and when the third FIFO is judged not to be empty, sequentially reading and outputting the original side data from the SDRAM according to the range sequence of the destination node, and storing the used base address into the first FIFO. The invention also discloses a device, equipment and a medium. The invention has high processing speed and can be flexibly configured according to the requirements.