摘要：【中文】当对包括耦合到多个字线和多个位线的多个存储单元的存储器件进行编程时，对多个字线中的两个相邻的第一和第二字线执行粗略编程。接下来，在对第一字线和第二字线执行粗略编程之后的第一时段期间，对多个位线中的未选择的位线进行预充电。另外，在第一时段的开始时导通未选择的位线和第二字线之间的沟道，并且在第一时段的结束之前关断该沟道。然后，在第一时段之后的第二时段期间，对第一字线执行精细编程。 【EN】When programming a memory device including a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, coarse programming is performed on two adjacent first and second word lines of the plurality of word lines. Next, unselected bit lines of the plurality of bit lines are precharged during a first period after performing the coarse programming on the first word line and the second word line. In addition, a channel between the unselected bit line and the second word line is turned on at the beginning of the first period, and is turned off before the end of the first period. Then, during a second period after the first period, fine programming is performed on the first word line.

摘要：【中文】公开了非易失性存储器件和控制方法。所述非易失性存储器件包括存储阵列、位线、多条字线、第一控制电路和第二控制电路。所述位线连接至存储阵列的第一存储串。所述多条字线连接至第一存储串的存储单元，每条字线连接至相应的存储单元。第一控制电路被配置为在预充电时间段期间向所述位线施加位线预脉冲信号。第二控制电路被配置为向被选择字线施加字线信号，并且向设置在选择栅极线和被选择字线之间的字线施加多个字线预脉冲信号。所述多个字线预脉冲信号的电压电平是递增的。 【EN】Disclosed are a nonvolatile memory device and a control method. The nonvolatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and a second control circuit. The bit line is connected to a first memory string of a memory array. The plurality of word lines are connected to the memory cells of the first memory string, and each word line is connected to a corresponding memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to the selected word line, and to apply a plurality of word line pre-pulse signals to the word lines disposed between the select gate line and the selected word line. The voltage levels of the plurality of word line pre-pulse signals are incremented.

摘要：【中文】在包括形成于衬底中的多个存储单元、顶部虚设储存区、底部虚设储存区、多个字线和多个位线的存储器件中，在第一时段期间，对所述多个位线中的选择的位线、所述衬底中的沟道区和所述衬底中的源极区进行预充电，并且在所述第一时段期间，向所述底部虚设储存区施加负预脉冲电压。在所述第一时段之后的第二时段期间，对所述多个存储单元中的选择的存储单元进行编程，其中，所述选择的存储单元被耦合到所述选择的位线和所述多个字线中的选择的字线。 【EN】In a memory device including a plurality of memory cells formed in a substrate, a top dummy storage region, a bottom dummy storage region, a plurality of word lines, and a plurality of bit lines, a selected bit line of the plurality of bit lines, a channel region in the substrate, and a source region in the substrate are precharged during a first period, and a negative pre-pulse voltage is applied to the bottom dummy storage region during the first period. Programming a selected memory cell of the plurality of memory cells during a second period of time after the first period of time, wherein the selected memory cell is coupled to the selected bit line and a selected word line of the plurality of word lines.

摘要：【中文】公开了非易失性存储器件。该非易失性存储器件包括存储阵列、多个字线、多个虚设字线、第一控制电路和第二控制电路。所述多个字线是连接到存储阵列的存储串的多个顶部存储单元和多个底部存储单元的。所述多个虚设字线是连接到在所述多个顶部存储单元和所述多个底部存储单元之间连接的多个虚设存储单元的。第一控制电路被配置为在预充电时段期间，将位线预脉冲信号应用于位线。第二控制电路被配置为将选定的字线信号应用于选定的字线，将未选定的字线信号应用于未选定的字线，以及将负预脉冲信号应用于所述多个虚设字线。 【EN】Disclosed is a nonvolatile memory device. The nonvolatile memory device includes a memory array, a plurality of word lines, a plurality of dummy word lines, a first control circuit, and a second control circuit. The plurality of word lines are connected to a plurality of top memory cells and a plurality of bottom memory cells of a memory string of the memory array. The plurality of dummy word lines are connected to a plurality of dummy memory cells connected between the plurality of top memory cells and the plurality of bottom memory cells. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a selected word line signal to a selected word line, an unselected word line signal to an unselected word line, and a negative pre-pulse signal to the plurality of dummy word lines.

摘要：【中文】一种存储器件，包括：顶部选择单元、顶部虚设单元和存储单元串。所述顶部选择单元具有耦合到位线的第一端子以及耦合到顶部选择线的控制端子。所述顶部虚设单元具有耦合到顶部虚设字线的控制端子。所述存储单元串具有耦合到相应字线的控制端子。操作所述存储器件的方法包括：在编程操作之前，在向所述字线施加低电压的同时，向所述顶部虚设字线、所述顶部选择线和所述位线施加预脉冲电压，并且然后在向所述字线施加所述低电压的同时，向所述顶部虚设字线、所述顶部选择线和所述位线顺序地施加所述低电压。 【EN】A memory device, comprising: a top select cell, a top dummy cell, and a memory cell string. The top select cell has a first terminal coupled to a bit line and a control terminal coupled to a top select line. The top dummy cell has a control terminal coupled to a top dummy word line. The memory cell string has a control terminal coupled to a respective word line. The method of operating the memory device includes: prior to a program operation, applying a pre-pulse voltage to the top dummy word line, the top select line, and the bit line while applying a low voltage to the word line, and then sequentially applying the low voltage to the top dummy word line, the top select line, and the bit line while applying the low voltage to the word line.

摘要：【中文】本发明公开了一种利用双螺杆挤出反应制备聚酰胺树脂的方法：将二酰氯、二胺、有机溶剂和含有缚酸剂的水溶液加入到双螺杆反应挤出装置中进行反应，洗涤、干燥、收集打包，得到聚酰胺树脂。本发明还公开了另外一种制备方法：先将二酰氯、二胺、有机溶剂加入到双螺杆反应挤出装置预缩聚，然后加入含缚酸剂水溶液再缩聚，洗涤、干燥、收集打包，得到聚酰胺树脂。本发明结合界面缩聚的特点，采用可连续化批量生产的双螺杆反应挤出制备了高纯度聚酰胺树脂，不仅克服了目前工业上低温溶液缩聚法制备芳香族聚酰胺及其共聚物中溶剂和小分子盐等难以脱除而影响后续加工及产品性能的不足，工艺简单、环保、成本较低，且易于实现连续批量化稳定生产。 【EN】The invention discloses a method for preparing polyamide resin by using a double-screw extrusion reaction, which comprises the following steps: adding diacid chloride, diamine, an organic solvent and an aqueous solution containing an acid-binding agent into a double-screw reaction extrusion device for reaction, washing, drying, collecting and packaging to obtain the polyamide resin. The invention also discloses another preparation method: adding diacid chloride, diamine and an organic solvent into a double-screw reaction extrusion device for pre-polycondensation, then adding an acid-binding agent-containing aqueous solution for polycondensation, washing, drying, collecting and packaging to obtain the polyamide resin. The method combines the characteristics of interfacial polycondensation, adopts double screws which can be produced in batch continuously to prepare the high-purity polyamide resin by reactive extrusion, overcomes the defects that the subsequent processing and the product performance are influenced because the solvent, small molecular salt and the like in the aromatic polyamide and the copolymer thereof prepared by the low-temperature solution polycondensation method in the prior industry are difficult to remove, and has simple process, environmental protection and lower cost, and is easy to realize continuous batch stable production.

摘要：【中文】公开了一种对三维(3D)NAND存储器件执行编程操作的方法。该方法使得能够去除在预充电阶段期间在3D NAND存储器件的未选定串的中间虚设存储单元的储存区域中俘获的残余电子，从而减小对与未选定串相邻的选定串的编程干扰。 【EN】A method of performing a program operation on a three-dimensional (3D) NAND memory device is disclosed. The method enables removal of residual electrons trapped in storage areas of intermediate dummy memory cells of unselected strings of the 3D NAND memory device during a precharge phase, thereby reducing program disturb on selected strings adjacent to the unselected strings.

摘要：【中文】一种存储器包括上堆叠体和下堆叠体。上堆叠体包括第一上虚设字线。下堆叠体包括第一下虚设字线。一种用于降低存储器的编程干扰的方法包括调整施加至第一上虚设字线的第一上偏置电压和/或第一上虚设字线的第一上阈值电压，以调整第一上偏置电压与第一上阈值电压之间的第一差值；以及调整施加至第一下虚设字线的第一下偏置电压和/或第一下虚设字线的第一下阈值电压，以调整第一下偏置电压与第一下阈值电压之间的第二差值。 【EN】A memory includes an upper stack and a lower stack. The upper stack includes a first upper dummy word line. The lower stack includes a first lower dummy word line. A method for reducing program disturb of a memory includes adjusting a first upper bias voltage applied to a first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.