摘要：【中文】本公开提供了一种半导体器件的形成方法。本公开实施例对形成连接源区、漏区和栅极结构与互连结构的导电结构的方法进行改进，使连接到源区和漏区的第一导电结构和第二导电结构与连接到栅极结构的第三导电结构在不同的步骤中形成，避免现有工艺过程中栅极结构与导电结构间形成缺陷而导致接触电阻异常，进而导致半导体器件失效的问题，同时，还能够避免连接栅极结构、连接源区和连接漏区的导电结构之间的距离过近而形成短路，提高半导体器件的良率。 【EN】The present disclosure provides a method of forming a semiconductor device. The embodiment of the disclosure improves a method for forming a conductive structure for connecting a source region, a drain region, a gate structure and an interconnection structure, so that a first conductive structure and a second conductive structure connected to the source region and the drain region and a third conductive structure connected to the gate structure are formed in different steps, the problem that in the prior art, contact resistance is abnormal due to defects formed between the gate structure and the conductive structures, and further a semiconductor device fails is solved, meanwhile, short circuit caused by too close distance among the conductive structures connected with the gate structure, the source region and the drain region can be avoided, and the yield of the semiconductor device is improved.

摘要：【中文】本申请公开了一种密钥更新方法、装置及设备，包括：物联网设备目标配置参数，该目标配置参数可以至少包括用于指示密钥集合中的目标密钥的第一指示信息，该密钥集合可以预先存储于该物联网设备，并且，该密钥集合包括多个不同的密钥；物联网设备将自身的密钥配置参数更新为获取的目标配置参数，该密钥配置参数用于指示物联网设备的通信密钥。可见，更新密钥的过程中，目标密钥并没有在物联网与网络之间进行传输，所传输的是目标配置参数，从而提高了密钥更新的安全性。 【EN】The application discloses a method, a device and equipment for updating a secret key, which comprise the following steps: the target configuration parameters of the internet of things device at least comprise first indication information for indicating a target key in a key set, wherein the key set can be stored in the internet of things device in advance, and comprises a plurality of different keys; the internet of things equipment updates the key configuration parameters of the internet of things equipment into the acquired target configuration parameters, and the key configuration parameters are used for indicating the communication keys of the internet of things equipment. Therefore, in the process of updating the key, the target key is not transmitted between the Internet of things and the network, and the target configuration parameters are transmitted, so that the security of updating the key is improved.

摘要：【中文】本发明提供一种半导体结构及其形成方法，半导体结构的形成方法包括：提供衬底；在所述衬底上形成多个分立的鳍部；形成覆盖所述鳍部顶面和侧壁的氧化层；对所述氧化层进行氮化处理，形成保形覆盖所述鳍部的鳍部保护层；形成所述鳍部保护层之后，对所述鳍部掺杂离子，以调整阈值电压；形成横跨所述鳍部的栅极结构，所述栅极结构覆盖所述鳍部的部分顶面和部分侧壁。本发明实施例先对鳍部进行热氧化处理再进行掺杂，与先掺杂再进行热氧化的工艺相比，能够避免热氧化过程中掺杂离子扩散造成的掺杂损失，且所述鳍部保护层为氮化处理形成，即所述鳍部保护层为氮化层，所述氮化层能够作为阻止掺杂离子扩散的阻障。 【EN】The invention provides a semiconductor structure and a forming method thereof, wherein the forming method of the semiconductor structure comprises the following steps: providing a substrate; forming a plurality of discrete fin portions on the substrate; forming an oxide layer covering the top surface and the side wall of the fin part; performing nitridation treatment on the oxide layer to form a fin part protection layer which conformally covers the fin part; after the fin portion protection layer is formed, doping ions into the fin portion to adjust threshold voltage; and forming a gate structure crossing the fin part, wherein the gate structure covers part of the top surface and part of the side wall of the fin part. In the embodiment of the invention, the thermal oxidation treatment is firstly carried out on the fin part and then the doping is carried out, compared with the process of carrying out the thermal oxidation after the doping, the doping loss caused by the diffusion of the doping ions in the thermal oxidation process can be avoided, and the fin part protective layer is formed by the nitridation treatment, namely the fin part protective layer is a nitrided layer which can be used as a barrier for preventing the diffusion of the doping ions.

摘要：【中文】一种半导体器件及其形成方法，方法包括：提供衬底；在所述衬底上形成第一栅极结构和源漏掺杂层，所述源漏掺杂层位于第一栅极结构两侧；在所述衬底上形成介质层，所述介质层覆盖第一栅极结构和源漏掺杂层；在介质层内形成暴露出源漏掺杂层的第一沟槽，所述第一沟槽包括底部区和位于底部区上的顶部区，所述顶部区尺寸大于所述底部区尺寸，所述顶部区侧壁相对于底部区侧壁凸出；在第一沟槽底部区内形成第一导电结构；形成第一导电结构后，在第一沟槽顶部区内形成绝缘层，所述绝缘层材料和介质层材料不同；形成绝缘层后，在介质层内形成与第一栅极结构相连的第二导电结构。所述方法提高了半导体器件的性能。 【EN】A semiconductor device and a method of forming the same, the method comprising: providing a substrate; forming a first grid structure and a source-drain doping layer on the substrate, wherein the source-drain doping layer is positioned on two sides of the first grid structure; forming a dielectric layer on the substrate, wherein the dielectric layer covers the first gate structure and the source-drain doping layer; forming a first groove exposing a source-drain doped layer in the dielectric layer, wherein the first groove comprises a bottom region and a top region positioned on the bottom region, the size of the top region is larger than that of the bottom region, and the side wall of the top region is protruded relative to the side wall of the bottom region; forming a first conductive structure in the bottom region of the first trench; after the first conductive structure is formed, forming an insulating layer in the top area of the first groove, wherein the material of the insulating layer is different from that of the dielectric layer; and after the insulating layer is formed, forming a second conductive structure connected with the first grid structure in the dielectric layer. The method improves the performance of the semiconductor device.

摘要：【中文】一种半导体器件及其形成方法，方法包括：提供衬底；在衬底上形成第一栅极结构和源漏掺杂层，源漏掺杂层位于第一栅极结构两侧；在衬底上形成介质层，介质层覆盖第一栅极结构和源漏掺杂层；在介质层内形成暴露出第一栅极结构的第一沟槽，第一沟槽包括底部区和位于底部区上的顶部区，在沿平行于衬底表面方向上，顶部区尺寸大于底部区尺寸，所述顶部区侧壁相对于所述底部区侧壁凹陷；在第一沟槽底部区内形成第一导电结构；形成第一导电结构后，在第一沟槽顶部区内形成绝缘层，绝缘层材料和介质层材料不同；以绝缘层为掩膜，在绝缘层两侧的介质层内形成暴露出源漏掺杂层的凹槽；在凹槽内形成第二导电结构。所述方法提高了半导体器件的性能。 【EN】A semiconductor device and a method of forming the same, the method comprising: providing a substrate; forming a first grid structure and a source-drain doping layer on a substrate, wherein the source-drain doping layer is positioned on two sides of the first grid structure; forming a dielectric layer on the substrate, wherein the dielectric layer covers the first gate structure and the source-drain doping layer; forming a first groove exposing the first grid structure in the dielectric layer, wherein the first groove comprises a bottom area and a top area positioned on the bottom area, the size of the top area is larger than that of the bottom area along the direction parallel to the surface of the substrate, and the side wall of the top area is recessed relative to the side wall of the bottom area; forming a first conductive structure in the bottom region of the first trench; after the first conductive structure is formed, an insulating layer is formed in the top area of the first groove, and the material of the insulating layer is different from that of the dielectric layer; forming a groove exposing the source-drain doping layer in the dielectric layer on two sides of the insulating layer by taking the insulating layer as a mask; and forming a second conductive structure in the groove. The method improves the performance of the semiconductor device.

摘要：【中文】一种半导体器件及其形成方法，包括：提供基底，基底包括沿第一方向排列的第一区、第二区和第三区；第一区内具有第一掺杂层；第三区内具有第二掺杂层，第二掺杂层和第一掺杂层沿第一方向排布；第二区上具有第一栅极结构，第一栅极结构的延伸方向为与第一方向平行或垂直的第二方向，第一栅极结构的顶部具有接触区；在基底上第一介质层；在第一介质层内形成暴露出第一掺杂层和第二掺杂层的第一沟槽，第一沟槽包括沿平行于第二方向排布的第二子区，第二子区到第一栅极结构接触区的最小距离大于零；在第一沟槽内形成第一导电层；在第二子区的第一导电层表面形成第二导电层；在第一栅极结构的接触区上形成第三导电层。所述方法提高了半导体器件的性能。 【EN】A semiconductor device and a method of forming the same, comprising: providing a substrate, wherein the substrate comprises a first area, a second area and a third area which are arranged along a first direction; the first region is provided with a first doping layer; the third region is provided with a second doped layer, and the second doped layer and the first doped layer are arranged along the first direction; the second region is provided with a first gate structure, the extension direction of the first gate structure is a second direction parallel or vertical to the first direction, and the top of the first gate structure is provided with a contact region; a first dielectric layer on a substrate; forming a first groove exposing the first doping layer and the second doping layer in the first dielectric layer, wherein the first groove comprises second sub-regions arranged in a direction parallel to the second direction, and the minimum distance from the second sub-regions to the first gate structure contact region is greater than zero; forming a first conductive layer in the first trench; forming a second conductive layer on the surface of the first conductive layer of the second sub-area; a third conductive layer is formed on the contact region of the first gate structure. The method improves the performance of the semiconductor device.

摘要：【中文】一种半导体器件及其形成方法，方法包括：提供衬底，所述衬底内具有第一阱区，所述第一阱区内掺杂有第一离子，所述第一阱区上具有第一鳍部；所述衬底上具有隔离结构，所述隔离结构覆盖第一鳍部的部分侧壁，且隔离结构的顶部表面低于第一鳍部的顶部表面；形成横跨所述第一鳍部的多个分立的第一伪栅极结构，所述第一伪栅极结构位于第一鳍部的部分顶部表面和部分侧壁表面，所述第一伪栅极结构包括第一伪栅极层；在相邻所述第一伪栅极结构之间的第一鳍部内形成第一外延层；去除所述第一伪栅极层，在所述介质层内形成第一伪栅开口；在所述第一伪栅开口内形成绝缘层，且所述绝缘层的表面与介质层的表面齐平。所述方法形成的半导体器件的性能较好。 【EN】A semiconductor device and a method of forming the same, the method comprising: providing a substrate, wherein the substrate is internally provided with a first well region, first ions are doped in the first well region, and a first fin part is arranged on the first well region; the substrate is provided with an isolation structure, the isolation structure covers part of the side wall of the first fin part, and the top surface of the isolation structure is lower than that of the first fin part; forming a plurality of discrete first dummy gate structures across the first fin, the first dummy gate structures being located on a portion of a top surface and a portion of a sidewall surface of the first fin, the first dummy gate structures including a first dummy gate layer; forming a first epitaxial layer in the first fin part between the adjacent first dummy gate structures; removing the first dummy gate layer, and forming a first dummy gate opening in the dielectric layer; and forming an insulating layer in the first pseudo gate opening, wherein the surface of the insulating layer is flush with the surface of the dielectric layer. The semiconductor device formed by the method has better performance.

摘要：【中文】一种半导体器件及其形成方法，其中形成方法，包括：提供基底，所述基底上具有鳍部结构，所述鳍部结构包括底部区和位于底部区上的顶部区，顶部区包括沿基底表面法线方向重叠的若干层复合鳍部层，各复合鳍部层均包括第二鳍部层以及位于第二鳍部层表面的第一鳍部层；在所述基底上形成第一隔离结构，所述第一隔离结构覆盖鳍部结构的底部区侧壁和至少部分最底层的第二鳍部侧壁；在最底层的第二鳍部层内形成阻挡掺杂区，阻挡掺杂区内掺杂有阻挡离子；在鳍部结构的底部区顶部形成阈值离子掺杂区，阈值离子掺杂区内掺杂有阈值电压调节离子。所述方法形成的半导体器件性能较好。 【EN】A semiconductor device and a method of forming the same, wherein the method of forming includes: providing a substrate, wherein the substrate is provided with a fin part structure, the fin part structure comprises a bottom area and a top area positioned on the bottom area, the top area comprises a plurality of layers of composite fin part layers which are overlapped along the normal direction of the surface of the substrate, and each composite fin part layer comprises a second fin part layer and a first fin part layer positioned on the surface of the second fin part layer; forming a first isolation structure on the substrate, wherein the first isolation structure covers the side wall of the bottom region of the fin portion structure and at least part of the side wall of the bottommost second fin portion; forming a barrier doping region in the second fin layer at the bottommost layer, wherein barrier ions are doped in the barrier doping region; and forming a threshold ion doping area at the top of the bottom area of the fin portion structure, wherein threshold voltage adjusting ions are doped in the threshold ion doping area. The semiconductor device formed by the method has better performance.

摘要：【中文】一种半导体结构及其形成方法，形成方法包括：提供基底，基底包括衬底以及位于衬底上多个分立的鳍部，衬底上形成有第一栅极结构和第二栅极结构，第一栅极结构横跨鳍部的栅极结构且覆盖鳍部的部分顶部和部分侧壁，第二栅极结构位于鳍部延伸方向的相邻鳍部之间的衬底上，第一栅极结构和第二栅极结构露出的衬底上形成有第一介质层，第一介质层覆盖第一栅极结构和第二栅极结构的侧壁；去除第二栅极结构，在第一介质层内形成第一开口；在第一开口内填充介电材料，第一开口内的介电材料用于作为隔离结构。本发明实施例通过使隔离结构的材料为介电材料，使隔离结构具有绝缘性，有利于避免源漏掺杂层和隔离结构发生短接的问题。 【EN】A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate comprises a substrate and a plurality of discrete fin parts positioned on the substrate, a first grid structure and a second grid structure are formed on the substrate, the first grid structure stretches across the grid structure of the fin parts and covers partial top and partial side walls of the fin parts, the second grid structure is positioned on the substrate between the adjacent fin parts in the extending direction of the fin parts, a first dielectric layer is formed on the substrate exposed by the first grid structure and the second grid structure, and the first dielectric layer covers the side walls of the first grid structure and the second grid structure; removing the second grid structure and forming a first opening in the first dielectric layer; and filling the first opening with a dielectric material, wherein the dielectric material in the first opening is used as an isolation structure. According to the embodiment of the invention, the isolation structure is made of the dielectric material, so that the isolation structure has insulating property, and the problem of short circuit between the source-drain doping layer and the isolation structure is avoided.

摘要：【中文】一种半导体结构及其形成方法，形成方法包括：提供基底，所述基底包括衬底、凸出于所述衬底的鳍部、横跨所述鳍部的栅极结构以及位于所述栅极结构两侧鳍部内的源漏外延层；在所述栅极结构露出的衬底上形成保护层，所述保护层至少覆盖所述源漏外延层的部分侧壁，且露出所述源漏外延层的顶部；对所述保护层露出的源漏外延层进行离子掺杂处理。本发明实施例中所述保护层能够在对所述源漏外延层进行离子掺杂处理的步骤中，对所述源漏外延层的侧壁起到保护作用，从而有利于减小所述源漏外延层的晶格损伤，相应有利于改善所述源漏外延层的应力释放问题，进而提高载流子的迁移率，以进一步地提高半导体结构的电学性能。 【EN】A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate comprises a substrate, a fin part protruding out of the substrate, a grid electrode structure crossing the fin part and source drain epitaxial layers positioned in the fin parts on two sides of the grid electrode structure; forming a protective layer on the substrate exposed out of the gate structure, wherein the protective layer at least covers part of the side wall of the source-drain epitaxial layer and exposes the top of the source-drain epitaxial layer; and carrying out ion doping treatment on the source-drain epitaxial layer exposed out of the protective layer. In the embodiment of the invention, the protective layer can protect the side wall of the source-drain epitaxial layer in the step of carrying out ion doping treatment on the source-drain epitaxial layer, so that the crystal lattice damage of the source-drain epitaxial layer is favorably reduced, the stress release problem of the source-drain epitaxial layer is correspondingly favorably improved, the mobility of a carrier is further improved, and the electrical performance of a semiconductor structure is further improved.